Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-118 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
TEMP7[31:0] ← DEST[127:112]
∗ SRC[127:112];
DEST[15:0] ← TEMP0[31:16];
DEST[31:16] ← TEMP1[31:16];
DEST[47:32] ← TEMP2[31:16];
DEST[63:48] ← TEMP3[31:16];
DEST[79:64] ← TEMP4[31:16];
DEST[95:80] ← TEMP5[31:16];
DEST[111:96] ← TEMP6[31:16];
DEST[127:112] ← TEMP7[31:16];
Intel C/C++ Compiler Intrinsic Equivalent
PMULHW __m64 _mm_mulhi_pi16 (__m64 m1, __m64 m2)
PMULHW __m128i _mm_mulhi_epi16 ( __m128i a, __m128i b)
Flags Affected
None.
Numeric Exceptions
None.
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
(128-bit operations only) If a memory operand is not aligned on
a 16-byte boundary, regardless of segment.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#UD If CR0.EM[bit 2] = 1.
128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]
= 0. Execution of 128-bit instructions on a non-SSE2 capable
processor (one that is MMX technology capable) will result in the
instruction operating on the mm registers, not #UD.
#NM If CR0.TS[bit 3] = 1.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#PF(fault-code) If a page fault occurs.
#AC(0) (64-bit operations only) If alignment checking is enabled and an
unaligned memory reference is made while the current privilege
level is 3.