Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-51

INSTRUCTION FORMATS AND ENCODINGS

memory, register 0100 0RXB 0000 1111 : 1100 000w : mod

reg r/m

memory8, bytereg 0100 1RXB 0000 1111 : 1100 0000 : mod

bytereg r/m

memory64, qwordreg 0100 1RXB 0000 1111 : 1100 0001 : mod

qwordreg r/m

XCHG – Exchange Register/Memory with

register1 with register2 1000 011w : 11 reg1 reg2

AX or EAX with register 1001 0 reg

memory with register 1000 011w : mod reg r/m

XLAT/XLATB – Table Look-up Translation

AL to byte DS:[(E)BX + unsigned AL] 1101 0111

AL to byte DS:[RBX + unsigned AL] 0100 1000 1101 0111

XOR – Logical Exclusive OR

register1 to register2 0100 0RXB 0011 000w : 11 reg1 reg2

byteregister1 to byteregister2 0100 0R0B 0011 0000 : 11 bytereg1

bytereg2

qwordregister1 to qwordregister2 0100 1R0B 0011 0001 : 11 qwordreg1

qwordreg2

register2 to register1 0100 0R0B 0011 001w : 11 reg1 reg2

byteregister2 to byteregister1 0100 0R0B 0011 0010 : 11 bytereg1

bytereg2

qwordregister2 to qwordregister1 0100 1R0B 0011 0011 : 11 qwordreg1

qwordreg2

memory to register 0100 0RXB 0011 001w : mod reg r/m

memory8 to byteregister 0100 0RXB 0011 0010 : mod bytereg r/m

memory64 to qwordregister 0100 1RXB 0011 0011 : mod qwordreg r/m

byteregister to memory8 0100 0RXB 0011 0000 : mod bytereg r/m

qwordregister to memory8 0100 1RXB 0011 0001 : mod qwordreg r/m

immediate to register 0100 000B 1000 00sw : 11 110 reg : imm

Table B-15. General Purpose Instruction Formats and Encodings

for 64-Bit Mode (Contd.)

Instruction and Format Encoding