Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-46 Vol. 2B

INSTRUCTION FORMATS AND ENCODINGS

quadregister by immediate count 0100 100B 1100 0001 : 11 100 quadreg :

imm8

memory by immediate count 0100 00XB 1100 000w : mod 100 r/m : imm8

memory8 by immediate count 0100 00XB 1100 0000 : mod 100 r/m : imm8

memory64 by immediate count 0100 10XB 1100 0001 : mod 100 r/m : imm8

SHLD – Double Precision Shift Left

reg1 : imm8

qwordregister by immediate8 0100 1R0B 0000 1111 : 1010 0100 : 11

qworddreg2 qwordreg1 : imm8

memory by immediate count 0100 0RXB 0000 1111 : 1010 0100 : mod reg

r/m : imm8

memory64 by immediate8 0100 1RXB 0000 1111 : 1010 0100 : mod

qwordreg r/m : imm8

reg1

quadregister by CL 0100 1R0B 0000 1111 : 1010 0101 : 11

quadreg2 quadreg1

memory by CL 0100 00XB 0000 1111 : 1010 0101 : mod reg

r/m

memory64 by CL 0100 1RXB 0000 1111 : 1010 0101 : mod

quadreg r/m

SHR – Shift Right

byteregister by 1 0100 000B 1101 0000 : 11 101 bytereg

qwordregister by 1 0100 100B 1101 0001 : 11 101 qwordreg

memory by 1 0100 00XB 1101 000w : mod 101 r/m

memory8 by 1 0100 00XB 1101 0000 : mod 101 r/m

memory64 by 1 0100 10XB 1101 0001 : mod 101 r/m

byteregister by CL 0100 000B 1101 0010 : 11 101 bytereg

qwordregister by CL 0100 100B 1101 0011 : 11 101 qwordreg

Table B-15. General Purpose Instruction Formats and Encodings

for 64-Bit Mode (Contd.)

Instruction and Format Encoding