Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-14 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
short 1110 1011 : 8-bit displacement
direct 1110 1001 : full displacement
register indirect 1111 1111 : 11 100 reg
memory indirect 1111 1111 : mod 100 r/m
JMP – Unconditional Jump (to other segment)
direct intersegment 1110 1010 : unsigned full offset, selector
indirect intersegment 1111 1111 : mod 101 r/m
LAHF – Load Flags into AHRegister 1001 1111
LAR – Load Access Rights Byte
from register 0000 1111 : 0000 0010 : 11 reg1 reg2
from memory 0000 1111 : 0000 0010 : mod reg r/m
LDS – Load Pointer to DS 1100 0101 : mod
A
reg r/m
LEA – Load Effective Address 1000 1101 : mod
A
reg r/m
LEAVE – High Level Procedure Exit 1100 1001
LES – Load Pointer to ES 1100 0100 : mod
A
reg r/m
LFS – Load Pointer to FS 0000 1111 : 1011 0100 : mod
A
reg r/m
LGDT – Load Global Descriptor Table Register 0000 1111 : 0000 0001 : mod
A
010 r/m
LGS – Load Pointer to GS 0000 1111 : 1011 0101 : mod
A
reg r/m
LIDT – Load Interrupt Descriptor Table
Register
0000 1111 : 0000 0001 : mod
A
011 r/m
LLDT – Load Local Descriptor Table Register
LDTR from register 0000 1111 : 0000 0000 : 11 010 reg
LDTR from memory 0000 1111 : 0000 0000 : mod 010 r/m
LMSW – Load Machine Status Word
from register 0000 1111 : 0000 0001 : 11 110 reg
from memory 0000 1111 : 0000 0001 : mod 110 r/m
LOCK – Assert LOCK# Signal Prefix 1111 0000
LODS/LODSB/LODSW/LODSD – Load String
Operand
1010 110w
LOOP – Loop Count 1110 0010 : 8-bit displacement
Table B-13. General Purpose Instruction Formats and Encodings
for Non-64-Bit Modes (Contd.)
Instruction and Format Encoding