Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-406 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
XCHG—Exchange Register/Memory with Register
Description
Exchanges the contents of the destination (first) and source (second) operands. The
operands can be two general-purpose registers or a register and a memory location.
If a memory operand is referenced, the processor’s locking protocol is automatically
implemented for the duration of the exchange operation, regardless of the presence
Opcode Instruction
64-Bit
Mode
Compat/
Leg
Mode Description
90+rw XCHG AX, r16 Valid Valid Exchange r16 with AX.
90+rw XCHG r16, AX Valid Valid Exchange AX with r16.
90+rd XCHG EAX, r32 Valid Valid Exchange r32 with EAX.
REX.W +
90+rd
XCHG RAX, r64 Valid N.E. Exchange r64 with RAX.
90+rd XCHG r32, EAX Valid Valid Exchange EAX with r32.
REX.W +
90+rd
XCHG r64, RAX Valid N.E. Exchange RAX with r64.
86 /r XCHG r/m8, r8 Valid Valid Exchange r8 (byte register)
with byte from r/m8.
REX + 86 /r XCHG r/m8*, r8* Valid N.E. Exchange r8 (byte register)
with byte from r/m8.
86 /r XCHG r8, r/m8 Valid Valid Exchange byte from r/m8 with
r8 (byte register).
REX + 86 /r XCHG r8*, r/m8* Valid N.E. Exchange byte from r/m8 with
r8 (byte register).
87 /r XCHG r/m16, r16 Valid Valid Exchange r16 with word from
r/m16.
87 /r XCHG
r16, r/m16 Valid Valid Exchange word from r/m16
with r16.
87 /r XCHG r/m32, r32 Valid Valid Exchange r32 with doubleword
from r/m32.
REX.W + 87 /r XCHG r/m64, r64 Valid N.E. Exchange r64 with quadword
from r/m64.
87 /r XCHG r32, r/m32 Valid Valid Exchange doubleword from
r/m32 with r32.
REX.W + 87 /r XCHG r64, r/m64 Valid N.E. Exchange quadword from
r/m64 with r64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix
is used: AH, BH, CH, DH.