Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-2 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
NEG—Two's Complement Negation
Description
Replaces the value of operand (the destination operand) with its two's complement.
(This operation is equivalent to subtracting the operand from 0.) The destination
operand is located in a general-purpose register or a memory location.
This instruction can be used with a LOCK prefix to allow the instruction to be
executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix
in the form of REX.R permits access to additional registers (R8-R15). Using a REX
prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at
the beginning of this section for encoding data and limits.
Operation
IF DEST = 0
THEN CF ← 0;
ELSE CF ← 1;
FI;
DEST ← [– (DEST)]
Flags Affected
The CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF,
AF, and PF flags are set according to the result.
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
F6 /3 NEG r/m8 Valid Valid Two's complement negate
r/m8.
REX + F6 /3 NEG r/m8* Valid N.E. Two's complement negate
r/m8.
F7 /3 NEG r/m16 Valid Valid Two's complement negate
r/m16.
F7 /3 NEG r/m32 Valid Valid Two's complement negate
r/m32.
REX.W + F7 /3 NEG r/m64 Valid N.E. Two's complement negate
r/m64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix
is used: AH, BH, CH, DH.