Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-295
INSTRUCTION SET REFERENCE, N-Z
SGDT—Store Global Descriptor Table Register
Description
Stores the content of the global descriptor table register (GDTR) in the destination
operand. The destination operand specifies a memory location.
In legacy or compatibility mode, the destination operand is a 6-byte memory loca-
tion. If the operand-size attribute is 16 bits, the limit is stored in the low 2 bytes and
the 24-bit base address is stored in bytes 3-5, and byte 6 is zero-filled. If the
operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the
low 2 bytes of the memory location and the 32-bit base address is stored in the high
4 bytes.
In IA-32e mode, the operand size is fixed at 8+2 bytes. The instruction stores an 8-
byte base and a 2-byte limit.
SGDT is useful only by operating-system software. However, it can be used in appli-
cation programs without causing an exception to be generated. See
“LGDT/LIDT—Load Global/Interrupt Descriptor Table Register” in Chapter 3, Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for information
on loading the GDTR and IDTR.
IA-32 Architecture Compatibility
The 16-bit form of the SGDT is compatible with the Intel 286 processor if the upper
8 bits are not referenced. The Intel 286 processor fills these bits with 1s; the
Pentium 4, Intel Xeon, P6 processor family, Pentium, Intel486, and Intel386™
processors fill these bits with 0s.
Operation
IF instruction is SGDT
IF OperandSize
= 16
THEN
DEST[0:15] ← GDTR(Limit);
DEST[16:39] ← GDTR(Base); (* 24 bits of base address stored *)
DEST[40:47] ← 0;
ELSE IF (32-bit Operand Size)
DEST[0:15] ← GDTR(Limit);
Opcode* Instruction
64-Bit
Mode
Compat/
Leg
Mode Description
0F 01 /0 SGDT m Valid Valid Store GDTR to m.
NOTES:
* See IA-32 Architecture Compatibility section below.