Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-244 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
THEN IF (ECX[30:0]
= 18:25
EAX ← PMC(ECX[30:0])[31:0]; (* 32-bit read *)
EDX ← 0;
FI;
ELSE (* Invalid PMC index in ECX[30:0], see Table 4-4
. *)
GP(0);
FI;
ELSE (* CR4.PCE = 0 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
#GP(0);
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0) If the current privilege level is not 0 and the PCE flag in the CR4
register is clear.
If an invalid performance counter index is specified (see
Table 4-2).
(Pentium 4 and Intel Xeon processors) If the value in ECX[30:0]
is not within the valid range.
Real-Address Mode Exceptions
#GP If an invalid performance counter index is specified (see
Table 4-2).
(Pentium 4 and Intel Xeon processors) If the value in ECX[30:0]
is not within the valid range.
Virtual-8086 Mode Exceptions
#GP(0) If the PCE flag in the CR4 register is clear.
If an invalid performance counter index is specified (see
Table 4-2).
(Pentium 4 and Intel Xeon processors) If the value in ECX[30:0]
is not within the valid range.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.