Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-76 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
SQRTPD—Compute Square Roots of
Packed Double-Precision Floating-
Point Values
xmmreg to xmmreg 0110 0110:0000 1111:0101 0001:11 xmmreg1
xmmreg 2
mem to xmmreg 0110 0110:0000 1111:0101 0001: mod xmmreg r/m
SQRTSD—Compute Square Root of
Scalar Double-Precision Floating-
Point Value
xmmreg to xmmreg 1111 0010:0000 1111:0101 0001:11 xmmreg1
xmmreg 2
mem to xmmreg 1111 0010:0000 1111:0101 0001: mod xmmreg r/m
SUBPD—Subtract Packed Double-
Precision Floating-Point Values
xmmreg to xmmreg 0110 0110:0000 1111:0101 1100:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0101 1100: mod xmmreg r/m
SUBSD—Subtract Scalar Double-
Precision Floating-Point Values
xmmreg to xmmreg 1111 0010:0000 1111:0101 1100:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0010:0000 1111:0101 1100: mod xmmreg r/m
UCOMISD—Unordered Compare
Scalar Ordered Double-Precision
Floating-Point Values and Set
EFLAGS
xmmreg to xmmreg 0110 0110:0000 1111:0010 1110:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0010 1110: mod xmmreg r/m
UNPCKHPD—Unpack and Interleave
High Packed Double-Precision
Floating-Point Values
xmmreg to xmmreg 0110 0110:0000 1111:0001 0101:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0001 0101: mod xmmreg r/m
Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format Encoding