Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-149
INSTRUCTION SET REFERENCE, N-Z
PSHUFB — Packed Shuffle Bytes
Description
PSHUFB performs in-place shuffles of bytes in the destination operand (the first
operand) according to the shuffle control mask in the source operand (the second
operand). The instruction permutes the data in the destination operand, leaving the
shuffle mask unaffected. If the most significant bit (bit[7]) of each byte of the shuffle
control mask is set, then constant zero is written in the result byte. Each byte in the
shuffle control mask forms an index to permute the corresponding byte in the desti-
nation operand. The value of each index is the least significant 4 bits (128-bit opera-
tion) or 3 bits (64-bit operation) of the shuffle control byte. Both operands can be
MMX register or XMM registers. When the source operand is a 128-bit memory
operand, the operand must be aligned on a 16-byte boundary or a general-protection
exception (#GP) will be generated.
In 64-bit mode, use the REX prefix to access additional registers.
Operation
PSHUFB with 64 bit operands:
for i = 0 to 7 {
if (SRC[(i * 8)+7] == 1 ) then
DEST[(i*8)+7...(i*8)+0] <- 0;
else
index[2..0] <- SRC[(i*8)+2 .. (i*8)+0];
DEST[(i*8)+7...(i*8)+0] <- DEST[(index*8+7)..(index*8+0)];
endif;
}
PSHUFB with 128 bit operands:
for i = 0 to 15 {
if (SRC[(i * 8)+7] == 1 ) then
DEST[(i*8)+7..(i*8)+0] <- 0;
else
index[3..0] <- SRC[(i*8)+3 .. (i*8)+0];
DEST[(i*8)+7..(i*8)+0] <- DEST[(index*8+7)..(index*8+0)];
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
0F 38 00 /r PSHUFB mm1,
mm2/m64
Valid Valid Shuffle bytes in mm1
according to contents of
mm2/m64.
66 0F 38 00 /r PSHUFB xmm1,
xmm2/m128
Valid Valid Shuffle bytes in xmm1
according to contents of
xmm2/m128.