Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-87
INSTRUCTION FORMATS AND ENCODINGS
mem to xmmreg 01100110:00001111:01111101: mod xmmreg
r/m
HSUBPS—Sub horizontally packed SP FP
numbers XMM2/Mem to XMM1
xmmreg2 to xmmreg1 11110010:00001111:01111101:11 xmmreg1
xmmreg2
mem to xmmreg 11110010:00001111:01111101: mod xmmreg
r/m
Table B-29. Formats and Encodings for SSE3 Event Management Instructions
Instruction and Format Encoding
MONITOR—Set up a linear address range to
be monitored by hardware
eax, ecx, edx 0000 1111 : 0000 0001:11 001 000
MWAIT—Wait until write-back store
performed within the range specified by
the instruction MONITOR
eax, ecx 0000 1111 : 0000 0001:11 001 001
Table B-30. Formats and Encodings for SSE3 Integer and Move Instructions
Instruction and Format Encoding
FISTTP—Store ST in int16 (chop) and pop
m16int 11011 111 : mod
A
001 r/m
FISTTP—Store ST in int32 (chop) and pop
m32int 11011 011 : mod
A
001 r/m
FISTTP—Store ST in int64 (chop) and pop
m64int 11011 101 : mod
A
001 r/m
LDDQU—Load unaligned integer 128-bit
xmm, m128 11110010:00001111:11110000: mod
A
xmmreg
r/m
MOVDDUP—Move 64 bits representing one
DP data from XMM2/Mem to XMM1 and
duplicate
xmmreg2 to xmmreg1 11110010:00001111:00010010:11 xmmreg1
xmmreg2
Table B-28. Formats and Encodings of SSE3 Floating-Point Instructions (Contd.)
Instruction and Format Encoding