Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

A-2 Vol. 2B

OPCODE MAP

A.2 KEY TO ABBREVIATIONS

Operands are identified by a two-character code of the form Zz. The first character,

an uppercase letter, specifies the addressing method; the second character, a lower-

case letter, specifies the type of operand.

A.2.1 Codes for Addressing Method

The following abbreviations are used to document addressing methods:

A Direct address: the instruction has no ModR/M byte; the address of the

operand is encoded in the instruction. No base register, index register, or

scaling factor can be applied (for example, far JMP (EA)).

C The reg field of the ModR/M byte selects a control register (for example, MOV

(0F20, 0F22)).

D The reg field of the ModR/M byte selects a debug register (for example,

MOV (0F21,0F23)).

E A ModR/M byte follows the opcode and specifies the operand. The operand is

either a general-purpose register or a memory address. If it is a memory

address, the address is computed from a segment register and any of the

following values: a base register, an index register, a scaling factor, a

displacement.

F EFLAGS/RFLAGS Register.

G The reg field of the ModR/M byte selects a general register (for example, AX

(000)).

I Immediate data: the operand value is encoded in subsequent bytes of the

instruction.

J The instruction contains a relative offset to be added to the instruction

pointer register (for example, JMP (0E9), LOOP).

M The ModR/M byte may refer only to memory (for example, BOUND, LES,

LDS, LSS, LFS, LGS, CMPXCHG8B).

N The R/M field of the ModR/M byte selects a packed-quadword, MMX tech-

nology register.

O The instruction has no ModR/M byte. The offset of the operand is coded as a

word or double word (depending on address size attribute) in the instruction.

No base register, index register, or scaling factor can be applied (for example,