Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-239
INSTRUCTION SET REFERENCE, N-Z
RDMSR—Read from Model Specific Register
Description
Loads the contents of a 64-bit model specific register (MSR) specified in an index
register into registers EDX:EAX. The input value loaded into the index register is the
address of the MSR to be read. The EDX register is loaded with the high-order 32 bits
of the MSR and the EAX register is loaded with the low-order 32 bits. If fewer than 64
bits are implemented in the MSR being read, the values returned to EDX:EAX in
unimplemented bit locations are undefined. In non-64-bit mode, the index register is
specified in ECX. In 64-bit mode, the index register is specified in RCX and the higher
32-bits of RDX and RAX are cleared.
This instruction must be executed at privilege level 0 or in real-address mode; other-
wise, a general protection exception #GP(0) will be generated. Specifying a reserved
or unimplemented MSR address in ECX will also cause a general protection excep-
tion.
The MSRs control functions for testability, execution tracing, performance-moni-
toring, and machine check errors. Appendix B, “Model-Specific Registers (MSRs),” in
the Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, lists
all the MSRs that can be read with this instruction and their addresses. Note that
each processor family has its own set of MSRs.
The CPUID instruction should be used to determine whether MSRs are supported
(EDX[5]=1) before using this instruction.
IA-32 Architecture Compatibility
The MSRs and the ability to read them with the RDMSR instruction were introduced
into the IA-32 Architecture with the Pentium processor. Execution of this instruction
by an IA-32 processor earlier than the Pentium processor results in an invalid opcode
exception #UD.
See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 21 of
the Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, for
more information about the behavior of this instruction in VMX non-root operation.
Opcode* Instruction
64-Bit
Mode
Compat/
Leg Mode Description
0F 32 RDMSR Valid Valid Load MSR specified by ECX into
EDX:EAX.
REX.W + 0F 32 RDMSR Valid N.E. Load MSR specified by RCX into
RDX:RAX.
NOTES:
* See IA-32 Architecture Compatibility section below.