Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-150 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
endif
}
Intel C/C++ Compiler Intrinsic Equivalent
PSHUFB __m64 _mm_shuffle_pi8 (__m64 a, __m64 b)
PSHUFB __m128i _mm_shufflehi_epi16(__m128i a, int n)
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS,
ES, FS or GS segments.
(128-bit operations only) If not aligned on 16-byte boundary,
regardless of segment.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#PF(fault-code) If a page fault occurs.
#UD If CR0.EM = 1.
(128-bit operations only) If CR4.OSFXSR(bit 9) = 0.
If CPUID.SSSE3(ECX bit 9) = 0.
#NM If TS bit in CR0 is set.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#AC(0) (64-bit operations only) If alignment checking is enabled and
unaligned memory reference is made while the current privilege
level is 3.
Figure 4-6. PSHUB with 64-Bit Operands
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