Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

A-10 Vol. 2B
OPCODE MAP
Table A-2. One-byte Opcode Map: (08H — FFH) *
89ABCDEF
0ORPUSH
CS
i64
2-byte
escape
(Table A-3)
Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz
1 SBB PUSH
DS
i64
POP
DS
i64
Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz
2 SUB SEG=CS
(Prefix)
DAS
i64
Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz
3CMPSEG=DS
(Prefix)
AAS
i64
Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz
4DEC
i64
general register / REX
o64
Prefixes
eAX
REX.W
eCX
REX.WB
eDX
REX.WX
eBX
REX.WXB
eSP
REX.WR
eBP
REX.WRB
eSI
REX.WRX
eDI
REX.WRXB
5POP
d64
into general register
rAX/r8 rCX/r9 rDX/r10 rBX/r11 rSP/r12 rBP/r13 rSI/r14 rDI/r15
6PUSH
d64
Iz
IMUL
Gv, Ev, Iz
PUSH
d64
Ib
IMUL
Gv, Ev, Ib
INS/
INSB
Yb, DX
INS/
INSW/
INSD
Yz, DX
OUTS/
OUTSB
DX, Xb
OUTS/
OUTSW/
OUTSD
DX, Xz
7 Jcc
f64
, Jb- Short displacement jump on condition
S NS P/PE NP/PO L/NGE NL/GE LE/NG NLE/G
8MOVMOV
Ev, Sw
LEA
Gv, M
MOV
Sw, Ew
Grp 1A
1A
POP
d64
Ev
Eb, Gb Ev, Gv Gb, Eb Gv, Ev
9CBW/
CWDE/
CDQE
CWD/
CDQ/
CQO
CALLF
i64
Ap
FWAIT/
WAIT
PUSHF/D/Q
d64
/
Fv
POPF/D/Q
d64
/
Fv
SAHF LAHF
A TEST STOS/B
Yb, AL
STOS/W/D/Q
Yv, rAX
LODS/B
AL, Xb
LODS/W/D/Q
rAX, Xv
SCAS/B
AL, Yb
SCAS/W/D/Q
rAX, Xv
AL, Ib rAX, Iz
B MOV immediate word or double into word, double, or quad register
rAX/r8, Iv rCX/r9, Iv rDX/r10, Iv rBX/r11, Iv rSP/r12, Iv rBP/r13, Iv rSI/r14, Iv rDI/r15 , Iv
CENTERLEAVE
d64
RETF RETF INT 3 INT INTO
i64
IRET/D/Q
Iw, Ib Iw Ib
D ESC (Escape to coprocessor instruction set)
ECALL
f64
JMP IN OUT
Jz near
f64
Jz
far
i64
AP
short
f64
Jb
AL, DX eAX, DX DX, AL DX, eAX
F CLC STC CLI STI CLD STD
INC/DEC INC/DEC
Grp 4
1A
Grp 5
1A
NOTES:
*
All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of unde-
fined or reserved locations.