Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-352 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
SUBSD—Subtract Scalar Double-Precision Floating-Point Values
Description
Subtracts the low double-precision floating-point value in the source operand
(second operand) from the low double-precision floating-point value in the destina-
tion operand (first operand), and stores the double-precision floating-point result in
the destination operand. The source operand can be an XMM register or a 64-bit
memory location. The destination operand is an XMM register. The high quadword of
the destination operand remains unchanged. See Figure 11-4 in the Intel
®
64 and
IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a
scalar double-precision floating-point operation.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
DEST[63:0] ← DEST[63:0] − SRC[63:0];
(* DEST[127:64] unchanged *)
Intel C/C++ Compiler Intrinsic Equivalent
SUBSD __m128d _mm_sub_sd (m128d a, m128d b)
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.
#XM If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1.
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
F2 0F 5C
/r
SUBSD xmm1,
xmm2/m64
Valid Valid Subtracts the low double-
precision floating-point values in
xmm2/mem64 from xmm1.