Technical Product Specification

Chassis Power Sub-system Intel
®
Server Chassis P4000S Family TPS
Intel order number G22850-006 Revision 1.5
26
Figure 20. Output Voltage Timing
Table 21. Turn On/Off Timing
Item
Description
Min.
Max.
Units
T
sb_on_delay
Delay from AC being applied to 5VSB being
within regulation.
1500
ms
T
ac_on_delay
Delay from AC being applied to all output
voltages being within regulation.
2500
ms
T
vout_holdup
Time all output voltages stay within regulation
after loss of AC. Tested at 75% of maximum
load.
13
ms
T
pwok_holdup
Delay from loss of AC to de-assertion of PWOK.
Tested at 75% of maximum load.
12
ms
T
pson_on_delay
Delay from PSON
#
active to output voltages
within regulation limits.
5
400
ms
T
pson_pwok
Delay from PSON
#
deactivate to PWOK being
de-asserted.
50
ms
T
pwok_on
Delay from output voltages within regulation
limits to PWOK asserted at turn on.
100
500
ms
T
pwok_off
Delay from PWOK de-asserted to output
voltages (3.3V, 5V, 12V, -12V) dropping out of
regulation limits.
1
ms
T
pwok_low
Duration of PWOK being in the de-asserted state
during an off/on cycle using AC or the PSON
signal.
100
ms
T
sb_vout
Delay from 5VSB being in regulation to O/Ps
being in regulation at AC turn on.
10
1000
ms
Vout
10%
Vout
T
vout_rise
T
vout_on
T
vout_off
V1
V2
V3
V4