Technical Product Specification

Intel
®
Server Chassis P4000S Family TPS Chassis Power Sub-system
Revision 1.5 Intel order number G22850-006
23
2.1.6.3 Standby Output
The 5VSB output is present when an AC input greater than the power supply turn on voltage is
applied.
2.1.6.4 Voltage Regulation
The power supply output voltages stay within the following voltage limits when operating at
steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise.
These shall be measured at the output connectors.
Table 16. Voltage Regulation Limits
PARAMETER
TOLERANCE
MIN
NOM
MAX
UNITS
+3.3V
- 5%/+5%
+3.14
+3.30
+3.46
V
rms
+5V
- 5%/+5%
+4.75
+5.00
+5.25
V
rms
+12V1
- 5%/+5%
+11.40
+12.00
+12.60
V
rms
+12V2
- 5%/+5%
+11.40
+12.00
+12.60
V
rms
- 12V
- 10%/+10%
- 13.20
-12.00
-10.80
V
rms
+5VSB
- 5%/+5%
+4.75
+5.00
+5.25
V
rms
2.1.6.5 Dynamic Loading
The output voltages remain within limits specified for the step loading and capacitive loading
specified in the table below. The load transient repetition rate is tested between 50Hz and 5kHz
at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test
specification. The  step load may occur anywhere within the minimum load to the maximum
load conditions.
Table 17. Transient Load Requirements
Output
 Step Load Size
(See note 2)
Load Slew Rate
Test capacitive Load
+3.3V
6.0A
0.5 A/sec
970 F
+5V
4.0A
0.5 A/sec
400 F
12V1+12V2
18.0A
0.5 A/sec
2200 F
1,2
+5VSB
0.5A
0.5 A/sec
20 F
Notes:
1. Step loads on each 12V output may happen simultaneously.
2. The +12V should be tested with 2200F evenly split between the four +12V rails.
3. This will be tested over the range of load conditions in section 2.1.6.2.
2.1.6.6 Capacitive Loading
The power supply is stable and meets all requirements with the following capacitive loading
ranges.
Table 18. Capacitive Loading Conditions
Output
MIN
MAX
Units
+3.3V
250
5000
F
+5V
400
5000
F
+12V
500
8000
F