Technical Product Specification

Chassis Power Sub-system Intel
®
Server Chassis P4000S Family TPS
Intel order number G22850-006 Revision 1.5
52
Table 62. Timing Requirements
Item
Description
MIN
MAX
UNITS
T
vout_rise
Output voltage rise time
5.0 *
70 *
ms
Tsb_on_delay
Delay from AC being applied to 12VSBbeing
within regulation.
1500
ms
Tac_on_delay
Delay from AC being applied to all output
voltages being within regulation.
3000
ms
Tvout_holdup
Time 12V output voltage stays within
regulation after loss of AC at 70% load.
13
ms
Tpwok_holdup
Delay from loss of AC to de-assertion of
PWOK
12
ms
Tpson_on_delay
Delay from PSON# active to output voltages
within regulation limits.
5
400
ms
Tpson_pwok
Delay from PSON# deactivate to PWOK
being de-asserted.
5
ms
Tpwok_on
Delay from output voltages within regulation
limits to PWOK asserted at turn on.
100
500
ms
T pwok_off
Delay from PWOK de-asserted to output
voltages dropping out of regulation limits.
1
ms
Tpwok_low
Duration of PWOK being in the de-asserted
state during an off/on cycle using AC or the
PSON signal.
100
ms
Tsb_vout
Delay from 12VSBbeing in regulation to O/Ps
being in regulation at AC turn on.
50
1000
ms
T12VSB_holdup
Time the 12VSBoutput voltage stays within
regulation after loss of AC.
70
ms
* The 12VSBoutput voltage rise time shall be from 1.0ms to 25ms