Intel Xeon Processor MP Specification Update

34 Intel
®
Xeon
®
Processor MP Specification Update
Errata
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O50 Processor may hang under certain frequencies and 12.5% STPCLK# duty
cycle
Problem: If a system de-asserts STPCLK# at a 12.5% duty cycle, the processor is running below 2 GHz, and
the processor thermal control circuit (TCC) on-demand clock modulation is active, the processor
may hang. This erratum does not occur under the automatic mode of the TCC.
Implication: When this erratum occurs, the processor will hang.
Workaround: If use of the on-demand mode of the processor's TCC is desired in conjunction with STPCLK#
modulation, then assure that STPCLK# is not asserted at a 12.5% duty cycle.
Status: For the steppings effected, see the Summary Table of Changes.
O51 BPM[5:3]# V
IL
does not meet specification
Problem: The V
IL
for BPM[5:3]# is specified as 0.9 * GTLREF [V]. Due to this erratum the V
IL
for these
signals is 0.9 * GTLREF -.100 [V].
Implication: The processor requires a lower input voltage than specified to recognize a low voltage on the
BPM[5:3]# signals.
Workaround: When intending to drive the BPM[5:3]# signals low, ensure that the system provides a voltage
lower than 0.9 * GTLREF -.100 [V].
Status: For the steppings effected, see the Summary Table of Changes.
O52 STPCLK# signal assertion under certain conditions may cause a system
hang
Problem: The assertion of STPCLK# signal before a logical processor awakens from the “Wait-for-SIPI”
state for the first time, may cause a system hang. A processor supporting HT Technology may fail
to initialize appropriately, and may not issue a Stop Grant Acknowledge special bus cycle in
response to the second STPCLK# assertion.
Implication: When this erratum occurs in an HT Technology enabled system, it may cause a system hang.
Workaround: BIOS should initialize the second thread of the processor supporting HT Technology prior to
STPCLK# assertion. Additionally, it is possible for the BIOS to contain a workaround for this
erratum.
Status: For the steppings affected, see the Summary Table of Changes.
O53 Parity error in the L1 cache may cause the processor to hang
Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the
processor may hang while trying to evict the line.
Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any
commercially available software.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O54 The TCK input in the test access port (TAP) is sensitive to low clock edge
rates and prone to noise coupling onto TCK's rising or falling edges
Problem: TCK is susceptible to double clocking when low amplitude noise occurs on TCK edge, while it is
crossing the receiver's transition region. TAP failures tend to increase with increases in background
system noise.