Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

Embedded Voltage Regulator-Down (EmVRD) 11.0
January 2007 Design Guidelines for Embedded Implementations
9
1.0—EmVRD 11.0
EMTS
A document that defines the processor electrical, mechanical, and thermal specifications. See
your Intel representative for access to EMTS documents.
Processor Load Line
The ratio of voltage drop/current load as measured across the processor Vccsense and
Vsssense pins. The Dual-Core Intel Xeon processor LV specifies the processor load-line value,
RLL which incorporates a component the processor package, processor socket and the
motherboard impedance. Load Line references in this document assume Processor Load Line in
not explicitly noted otherwise.
PWM Pulse Width Modulation, EmVRD voltage resultor controller
RDS-ON MOSFET source to drain conduction resistance when biased
RSS Root Sum Square. A method of adding statistical variables.
Socket Load Line
Processor Loadline minus the Package and Socket impedance = the motherboard impedance.
The characteristic impedance of the motherboard power delivery circuit, in conjunction with
high frequency decoupling, bulk decoupling, and power plane impedance. Design compliance to
this parameter ensures that the processor motherboard voltage specifications minus the
processor socket are satisfied.
Dual-Core Intel
®
Xeon
®
Processor LV, and Dual-Core
Intel
®
Xeon
®
Processor ULV
and Intel
®
Celeron
®
Processor
1.66 GHz / 1.83 GHz processor
families
The embedded dual core, dual-processor/single-core, single processor (Intel
®
Celeron
®
Processor 1.66 GHz / 1.83 GHz) capable IA32 microprocessors.
Static Load Line
DC resistance at the defined regulation node. Defined as the quotient of voltage and current (V/
I) under steady state conditions. This value is configured by proper tuning of the PWM
controller voltage positioning circuit. In this document, the static load line is referenced at the
socket unless otherwise stated.
TDC
Voltage Regulator Thermal Design Current. The sustained DC current the voltage regulator
must support under the system defined cooling solution.
Thermal Monitor
A feature of the voltage regulator that sets the processor in a low power state when critical
EmVRD temperatures are reached, thereby reducing power and EmVRD temperature.
TOB
Vcc regulation tolerance band. Defines the voltage regulator’s 3*
σ voltage variation across
temperature, manufacturing variation, and age factors. Must be guaranteed by design through
component selection. Defined at processor maximum current and maximum VID levels.
TOS Time Overshoot
Dynamic Load Line
Transient Response equal to dV/di or Vdroop/Istep and is controlled by switching frequency,
decoupling capacitor selection, and motherboard layout parasitics. In this document, the
transient load line is referenced at the Vccsense and Vsssense unless otherwise stated.
V
CCP
Voltage provided to the processor to initiate power up and drive I/O buffer circuits
VID
Voltage Identification: A binary code supplied by the processor that determines the a reference
output voltage to the EmVRD controller. At zero amperes and the tolerance band at + 3*
σ, VID
is the voltage at the processor.
VOS V
CC
Overshoot
VRD Desktop Voltage Regulator Down. A Desktop VR circuit resident on the motherboard.
VRM Enterprise/Server Voltage Regulator Module that is socketed/pluggable to a motherboard.
EVRD Enterprise/Server Voltage Regulator Down circuit resident on the motherboard.
EmVRD Embedded Voltage Regulator Down. An Embedded VR circuit resident on the motherboard.
Vtt See V
CCP
Table 1. Glossary (Sheet 2 of 2)
Term Description