Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

Embedded Voltage Regulator-Down (EmVRD) 11.0
January 2007 Design Guidelines for Embedded Implementations
5
—EmVRD 11.0
Figures
1 Processor Load Line.................................................................................................. 12
2 Processor Load Transient Limits .................................................................................13
3 Examples of High Volume Manufacturing Load Line Violations.........................................15
4 Examples of High Volume Manufacturing Compliant Load Lines.......................................16
5 Processor D-VID Load Line Transition States................................................................19
6 EmVRD 11.0 D-VID Transition Timing States (12.5 mV VID Resolution)...........................21
7 Overshoot and Undershoot During Dynamic VID Validation ............................................ 22
8 Graphical Representation of Overshoot Parameters.......................................................24
9Example Processor V
CC
Overshoot Waveform ...............................................................25
10 Start-Up Sequence...................................................................................................31
11 Power-Off Timing Sequence.......................................................................................32
12 Start-Up Sequence Functional Block Diagram...............................................................33
13 D-VID Bus Topology.................................................................................................36
14 FORCEPR# Buffering ................................................................................................42
15 Layer 1 V
CC
Shape For Intel’s Reference Ten Layer Motherboard .....................................45
16 Layer 10 V
CC
Shape For Intel’s Reference Ten Layer Motherboard ...................................46
17 Layer 1 CPU Socket V
CC
/GND Routing For Intel’s Reference Ten Layer Motherboard..........47
Tables
1 Glossary ...................................................................................................................8
2 Related Documentation.............................................................................................10
3 Processor Load Line Equations ................................................................................... 11
4V
CC
Regulator Design Parameters...............................................................................12
5 Processor Load-Line Window......................................................................................14
6 Current Step Values for Transient Processor Load Line Testing .......................................14
7 D-VID Validation Summary Table...............................................................................22
8V
CC
Overshoot Terminology.......................................................................................23
9V
CC
Overshoot Specifications......................................................................................23
10 Intel Processor Current Release Values for Overshoot Testing ........................................23
11 Board Decoupling Requirements per CPU.....................................................................27
12 VCCP Specifications..................................................................................................29
13 VCCP Measurement Pins ........................................................................................... 29
14 VCCP Bypass Capacitors TD7: Regulation to Power Down Delay.....................................29
15 Start-Up and Power-Off Sequence Timing....................................................................32
16 VID Buffer And VID Bus Electrical Parameters..............................................................36
17 VR11 VID Table from 1.5 V to 0.81875 V ....................................................................37
18 VR_Ready Output Signal Specifications .......................................................................41
19 FORCEPR# Specifications ..........................................................................................42
20 Reference Board Layer Stack-up ................................................................................44