Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

EmVRD 11.0—8.0
Embedded Voltage Regulator-Down (EmVRD) 11.0
Design Guidelines for Embedded Implementations January 2007
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8.0 Output Protection
This section describes features that are built into the EmVRD controller to prevent
damage to itself, the processor, validation tools, or other system components. Intel
highly recommends that system designers choose a VR11 controller that supports
these features.
8.1 Over-Voltage Protection (OVP)
OVP is intended to protect the processor from high voltage damage that may lead to
failure, or a reduced processor life span. The OVP circuit is to monitor Vcc for an over-
voltage condition at the defined regulation pins. This voltage must never exceed
VID+200 mV under any condition and operation above this level defines an OVP
violation. In the event of an OVP violation, the V
CC
VR low side MOSFETs should be
driven on to protect the processor and the VR should de-assert VR_READY to shut
down the core supply voltage. Power cycling is required to re-start the system.
OVP at start-up should be fully functional with a trip level referenced to the boot VID of
1.1 V.
Operating at lower VID codes during Dynamic VID establishes low (invalid) OVP
thresholds which must not be used to initiate a system shut down. For example, there
is a time delay from transmission of a VID code to the VR reaction; this time lag may
result in a 200 mV delta from the reference VID at a functional voltage that will not
damage the processor. Because of these conditions, OVP functionality must be blanked
during the Dynamic VID state.
8.2 Over-Current Protection (OCP)
The DC-DC should be capable of withstanding a continuous, abnormally low resistance
on the output without damage or over-stress to the DC-DC. The OCP trip level should
be programmable by the DC-DC designer, typically 130 percent of rated output current.
If an OCP fault is detected, the VR should fold back or shut down, de-assert VR_READY
and reset the start up sequence.
Output current under this condition must be limited to avoid component damage and
violation of the EmVRD thermal specifications.