Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

EmVRD 11.0—6.0

Embedded Voltage Regulator-Down (EmVRD) 11.0

Design Guidelines for Embedded Implementations January 2007

6.2 VID_SEL: VID Table Selection

VID_SEL is an input on the VR11 controller determines which VID code table to use. It

is a static line that can be strapped or floated based on the particular manufacture’s

instructions. The VID_SEL pin will map the VID inputs to a VR10.x or VR11.0 voltage

definition table. The processor will always select the VR11.0 based VID table and

designers need to ensure the proper table is being used. This document assumes that

the VR11.0 table has been selected. A logic 0 = VR10 VID mode, logic 1= VR11.0 VID

mode. The EmVRD should sample VID_SEL during the TD1 time period at startup and

select the proper VID table definition (see Figure 10).

101110 1.03750

101111 1.02500

110000 1.01250

110001 1.00000

110010 0.98750

110011 0.97500

110100 0.96250

110101 0.95000

110110 0.93750

110111 0.92500

111000 0.91250

111001 0.90000

111010 0.88750

111011 0.87500

111100 0.86250

111101 0.85000

111110 0.83750

111111 0.82500

Table 17. VR11 VID Table from 1.5 V to 0.81875 V (Sheet 2 of 2)

VR 76543210VID<7-0>

CPU 543210 VID<5-0>