Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

EmVRD 11.0—4.0
Embedded Voltage Regulator-Down (EmVRD) 11.0
Design Guidelines for Embedded Implementations January 2007
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Figure 11. Power-Off Timing Sequence
Note: Timing is not to scale.
Table 15. Start-Up and Power-Off Sequence Timing
Start up Delay Parameters
Parameter Minimum Typical, Default Maximum
TD1 1 ms - 5 ms
TD2 0 ms 500 µs 5 ms
TD3 50 µs - 3 ms
TD4 0 µs 250 µs 2.5 ms
TD5 0 ms - 3 ms
TD6 500 µs
TD7 0 ms - 1 ms
PWM Vcc
V
TT
Vcc
VID [5:0]
VIDSELECT
VR_READY
A
N
D
TD7