Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

Embedded Voltage Regulator-Down (EmVRD) 11.0

January 2007 Design Guidelines for Embedded Implementations

4.0—EmVRD 11.0

input rails. If either the Vcc or power conversion rail fall below the UVLO thresholds,

the controller should shut down in an orderly manner and restart the start up

sequence.

4.4 Soft Start (SS)

The EmVRD controller will have a soft start function to limit inrush current into the

output capacitor bank and prevent false over current protection (OCP) trips. The soft

start should have a ramp of 500 s as an internally programmed default. A SS pin for

user programmability of SS ramp to extend the ramp to 1-5 ms is required. Consult

TD2 and TD4 parameters in Figure 10 and Section 15 for further details.

Figure 10. Start-Up Sequence

Notes:

1. TD2, TD4 voltage slopes are determined by soft start logic.

2. Timing not to scale.

TD1

TD3

Programmable

Soft Start

Ramp

Vcc = VID

Vcc = V

BOOT

PWM Vcc

Vcc

VID [5:0]

BSEL [2:0]

VR_READY

TD4TD2

TD5

VID code read

by controller

TD1 Delay initiated

only when PWM Vcc

and VTT are valid

BCLK [1:0]

BCLK [1 :0] Triggered

at end of TD5 Event

VIDSELECT

VID Table Configured

CPUPWRGD

Delay to ensure

PROCESSOR PWRGD

Does Not Initiate

until BCLK is stable

TD6