Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

EmVRD 11.0—2.0
Embedded Voltage Regulator-Down (EmVRD) 11.0
Design Guidelines for Embedded Implementations January 2007
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same voltage level. Since waveform A has zero overshoot amplitude margin, this
increase in Vzc due to manufacturing drift will yield a 20 mV overshoot violation which
will reduce the processor life span. To address this issue in validation, a voltage
margining technique can be employed to ensure overshoot amplitudes stay below a
safe value. This technique translates the specification baseline from VID to a EmVRD
validation baseline of Vzc + VOS_MAX, which defines a test limit for specification
compliance across the full TOB range:
Equation 4. Overshoot Voltage Limit
VOS < Vzc + VOS_MAX
Equation 4 is to be used during validation to ensure overshoot is in compliance to
specifications across high volume manufacturing variation. In addition, the overshoot
duration must be referenced to Vzc and cannot exceed this level by more than 25
µs.
Figure 8. Graphical Representation of Overshoot Parameters