Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

Embedded Voltage Regulator-Down (EmVRD) 11.0
January 2007 Design Guidelines for Embedded Implementations
23
2.0—EmVRD 11.0
Maximum overshoot is validated by monitoring the voltage across the recommended
test pins (defined in Section 2.2) while applying a current load release across the
socket V
CC
and V
SS
pin field. Amperage values for performing this validation under each
EmVRD design configuration are identified in Table 6. The platform voltage regulator
output filter must be stuffed with a sufficient quality and number of capacitors to
ensure that overshoot stays above VID for a time no longer than TOS_MAX and never
exceeds the maximum amplitude of VID+VOS_MAX. Measurements are to be taken
using an oscilloscope with a 20 MHz bandwidth. Boards in violation must be redesigned
for compliance to avoid processor damage.
To prevent processor damage, EmVRD designs should comply to overshoot
specifications across the full processor load line tolerance band window (see
Section 2.2). When validating a system’s overshoot, a single measurement is
statistically insignificant and cannot represent the response variation seen across the
entire high volume manufacturing population of EmVRD designs. A typical design may
fit in the processor load line window; however designs residing elsewhere in the
tolerance band distribution may violate the V
CC
overshoot specifications. Figure 8
provides an illustration of this concept.
A typical board will have the Vcc zero current voltage (Vzc) centered in the processor
load line window at VID-TOB; for this example consider waveform A and assume TOB is
20 mV. Now assume that the EmVRD has maximum overshoot amplitude of VOS_MAX
= 50 mV above VID. Under this single case, the overshoot aligns with the specification
limit and there is zero margin to violation. Under manufacturing variation Vzc can drift
to align with VID (waveform B). This drift will shift the overshoot waveform by the
Table 8. V
CC
Overshoot Terminology
Parameter Definition
VOS Measured peak overshoot voltage
VOSMAX Maximum specified overshoot voltage allowed above VID
TOS Measured overshoot time duration
TOSMAX Maximum specified overshoot time duration above VID
Vzc Zero current voltage: The voltage where the measured load line intercepts the voltage axis
Vzco Zero current offset from VID: Vzco = VID – Vzc
Table 9. V
CC
Overshoot Specifications
Parameter Specification
VOS_MAX mV
TOS_MAX µs
VOS Maximum = VID + VOS_MAX
TOS Maximum = TOS_MAX
Table 10. Intel Processor Current Release Values for Overshoot Testing
VR Configuration Starting Current Ending Current
Dynamic
Current Step
Dual-Core Intel
®
Xeon
®
Processor LV 23.6 A 36 A 12.4 A
Dual-Core Intel
®
Xeon
®
Processor ULV 13.3A 19A 6.6 A
Intel
®
Celeron
®
Processor 1.66 GHz /
1.83 GHz
23.6 A 36 A 12.4 A