Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

EmVRD 11.0—2.0
Embedded Voltage Regulator-Down (EmVRD) 11.0
Design Guidelines for Embedded Implementations January 2007
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2.5.2 D-VID Validation
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components and reflect the approximate performance of Intel products as measured by
those tests. Any difference in system hardware or software design or configuration may
affect actual performance. Buyers should consult other sources of information to
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visit Intel Performance Benchmark Limitations.
Intel processors are capable of generating numerous D-VID states and the EmVRD
must be designed to properly transition to and function at each possible VID voltage.
However, exhaustive validation of each state is unnecessary and impractical. Validation
can be simplified by verifying the EmVRD conforms to processor load line requirements,
tolerance band specifications, and D-VID timing requirements. Then, by default, each
processor D-VID state will be valid. The key variables for V
CC
under D-VID conditions
are processor loading, starting VID, ending VID, and V
CC
slew rate. The V
CC
slew rate is
defined by EmVRD bulk decoupling, the output inductors, the switching FET resistance
and the processor load. This indicates that the V
CC
slewing will have an exponential
behavior, where the response to code ‘n+1’ takes longer to settle than code ‘n’. As a
result, a test from maximum to minimum and from minimum to maximum will be
sufficient to guarantee slew rate requirements and VID code regulation.
To ensure support for any valid VID reference, testing should be performed from the
maximum EmVRD 11.0 voltage of 1.5 V to the minimum VID table value. For
Embedded VR11, use 0.825 V for the minimum value.
The EmVRD must ensure that the full table transition occurs within 50 microseconds of
the final VID code transmission. Slew rate timing is referenced from 0.4 V on the rising
edge of the initial VID code to the time the final voltage is settled within 5 mV of the
final Vcc value. Intel testing has noted a 10% change to the V
CC
slew rate between
EmVRD no load (5 A) and full load (VR_TDC) conditions. For this reason, the V
CC
slewing must be tested under both loading conditions.
During the D-VID test defined in the previous paragraph, V
CC
droop and undershoot
amplitudes must be limited to avoid processor damage and performance failures. If the
processor experiences a voltage undershoot due to D-VID transitions, an application
initiated di/dt droop can superimpose with this event and potentially violate minimum
voltage specifications. Droop during this D-VID test must be limited to 5 mV. This value
was derived by calculating EmVRD tolerance band improvements at the low D-VID
current and voltage values. If the processor experiences an overshoot due to D-VID
transitions, an application initiated di/dt overshoot can superimpose with this event and
potentially violate overshoot specifications. Overshoot is permitted, but must be
properly budgeted with respect to the specifications defined in Section 2.6.
Superposition of the dynamic VID overshoot event and the overshoot resulting from the
transient test defined in Section 2.6, must not exceed the amplitude and time
requirements defined in the overshoot specification.
2.5.2.1 VR11 Validation Summary
This exercise tests the EmVRD 11.0 functionality with 12.5 mV VID resolution. The use
of the Voltage Test Tool (VTT) is recommended to provide the synthetic loads and D-
VID control. Consult Figure 6 and Figure 7 for graphic representation of validation
requirements.
1. Constraints:
a. The 662.5 mV +/-5 mV transition must occur within 315 s (see Figure 6).
b. Start time is referenced to 0.4 V on the rising edge of the initial D-VID code.
c. End time is referenced to the steady state Vcc voltage after the final D-VID code.