Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

Embedded Voltage Regulator-Down (EmVRD) 11.0
January 2007 Design Guidelines for Embedded Implementations
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2.0—EmVRD 11.0
During a D-VID event, the processor load may not be capable of absorbing output
capacitor energy when the VID reference is lowered. As a result, reverse current may
flow into the AC-DC regulator’s input filter, potentially charging the input filter to a
voltage above the over voltage value. Upon detection of this condition, the AC-DC
regulator will react by shutting down the AC-DC regulator supply voltage. The EmVRD
and AC-DC filter must be designed to ensure this condition does not occur. In addition,
reverse current into the AC-DC regulator must not impair the operation of the EmVRD,
the AC-DC supply, or any other part of the system.
Under all functional conditions, including D-VID, the Vcc supply must satisfy load line
and overshoot constraints to avoid data corruption, system lock-up events, or system
blue-screen failures.
Figure 5. Processor D-VID Load Line Transition States
Vcc (Voltage)
Icc (Amperes)
Original VID
Load Line Window
Low Voltage VID
Load Line Window
1
2
3
4
5
D-VID Vmax
Load Line
Vmin Load Line
D- VID Vmin Load Line
Vmax Load Line