Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

Embedded Voltage Regulator-Down (EmVRD) 11.0
January 2007 Design Guidelines for Embedded Implementations
11
2.0—EmVRD 11.0
2.0 Processor V
CC
Requirements
2.1 Voltage and Current
A six-bit VID code supplied by the processor to the EmVRD controller determines the
reference output voltage as described in Section 6.1. The processor load lines in
Section 2.2 show the relationship between V
CC
and I
CC
for the processor at the
processor cores.
Intel performs exhaustive testing against multiple software applications and software
test vectors to identify valid processor V
CC
operating ranges. Failure to satisfy the
processor load line (RLL), load line tolerance band (TOB), and overshoot voltage
specifications (VOS) as shown in Section 2.3 and Section 2.6 may invalidate Intel
warranties and lead to premature processor failure, intermittent system lock-up (blue
screen), and/or data corruption.
2.2 Processor Load Line Definitions
To ensure processor reliability and performance, platform static and dynamic voltage
regulation must always be contained within the V
CCMAX
and V
CCMIN
processor load line
boundaries (known as the load line window). Processor load line compliance must be
guaranteed across 3*
σ component manufacturing tolerances, thermal variation, and
age degradation. Processor load line boundaries are defined by the equations in Table 3
and in conjunction with the processor design parameter values defined in Table 4. Load
line voltage tolerance is defined in Section 2.3. In the equations in Table 3, VID, RLL,
and TOB are known. Plotting V
CC
while varying I
CC
from 0 A to I
CCMAX
establishes the
V
CCMAX
and V
CCMIN
processor load lines, see Figure 1. V
CCMAX
establishes the maximum
DC processor load line boundary. Short AC transient bursts above the V
CCMAX
load line
are permitted; this condition is defined in Section 2.6. V
CCMIN
establishes the minimum
AC and DC voltage boundary.
Table 3. Processor Load Line Equations
Processor Load Line Equation
Equation 1. V
CCMAX
processor load line
V
CC
= VID +TOB - (RLL* I
CC
)
Equation 2. V
CCTYP
processor load line
V
CC
= VID - (RLL* I
CC
)
Equation 3. V
CCMIN
processor load line
V
CC
= VID - TOB - (RLL* I
CC
)