Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-63
INSTRUCTION FORMATS AND ENCODINGS
MOVAPS—Move Aligned Packed
Single-Precision Floating-Point Values
xmmreg2 to xmmreg1 0000 1111:0010 1000:11 xmmreg2 xmmreg1
mem to xmmreg1 0000 1111:0010 1000: mod xmmreg r/m
xmmreg1 to xmmreg2 0000 1111:0010 1001:11 xmmreg1 xmmreg2
xmmreg1 to mem 0000 1111:0010 1001: mod xmmreg r/m
MOVHLPS—Move Packed Single-
Precision Floating-Point Values High to
Low
xmmreg to xmmreg 0000 1111:0001 0010:11 xmmreg1 xmmreg2
MOVHPS—Move High Packed Single-
Precision Floating-Point Values
mem to xmmreg 0000 1111:0001 0110: mod xmmreg r/m
xmmreg to mem 0000 1111:0001 0111: mod xmmreg r/m
MOVLHPS—Move Packed Single-
Precision Floating-Point Values Low to
High
xmmreg to xmmreg 0000 1111:00010110:11 xmmreg1 xmmreg2
MOVLPS—Move Low Packed Single-
Precision Floating-Point Values
mem to xmmreg 0000 1111:0001 0010: mod xmmreg r/m
xmmreg to mem 0000 1111:0001 0011: mod xmmreg r/m
MOVMSKPS—Extract Packed Single-
Precision Floating-Point Sign Mask
xmmreg to r32 0000 1111:0101 0000:11 r32 xmmreg
MOVSS—Move Scalar Single-Precision
Floating-Point Values
xmmreg2 to xmmreg1 1111 0011:0000 1111:0001 0000:11 xmmreg2
xmmreg1
mem to xmmreg1 1111 0011:0000 1111:0001 0000: mod xmmreg
r/m
xmmreg1 to xmmreg2 1111 0011:0000 1111:0001 0001:11 xmmreg1
xmmreg2
xmmreg1 to mem 1111 0011:0000 1111:0001 0001: mod xmmreg
r/m
Table B-21. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format Encoding