user manual

ManualsBrandsIntel ManualsNetwork RouterNetwork Router 41210

Order Number: 278890-003US

Intel

41210 Serial to Parallel PCI

Bridge

Developer’s Manual

May 2005

Summary of content (120 pages)

PAGE 1
Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual May 2005 Order Number: 278890-003US
PAGE 2
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT.
PAGE 3
Contents Contents 1 Introduction..................................................................................................................................11 1.1 1.2 1.3 1.4 1.5 2 Signal Description .......................................................................................................................13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3 3.3 3.4 Initialization ..............................................................................................................
PAGE 4
Contents 5.4 5.5 5.6 6 Transaction Ordering .................................................................................................................. 51 6.1 6.2 6.3 7 Upstream Transaction Ordering ......................................................................................... 51 Downstream Transaction Ordering..................................................................................... 52 Relaxed Ordering/No-Snoop Support.......................................................
PAGE 5
Contents 12.2.6 Offset 0Ch: CLS—Cache-Line Size.......................................................................81 12.2.7 Offset 0Dh: PMLT—Primary Master Latency Timer ..............................................81 12.2.8 Offset 0Eh: HEADTYP—Header Type...................................................................81 12.2.9 Offset 18h: BNUM—Bus Numbers ........................................................................82 12.2.10 Offset 1Bh: SMLT—Secondary Master Latency Timer..............
PAGE 6
Contents 12.2.53 Offset 108h: ERRUNC_MSK—PCI Express* Uncorrectable Error Mask.................................................................................... 106 12.2.54 Offset 10Ch: ERRUNC_SEV—PCI Express* Uncorrectable Error Severity....................................................................................................... 107 12.2.55 Offset 110h: ERRCOR_STS—PCI Express* Correctable Error Status ......................................................................................
PAGE 7
Contents Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 ODT Signals ...............................................................................................................................14 PCI Express* Interface Pins .......................................................................................................15 PCI Interface Pins..............................................................
PAGE 8
Contents 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 8 Offset 2Ch: PMLU32—Prefetchable Memory Limit Upper 32 Bits ............................................. 87 Offset 30h: IOBLU16—I/O Base and Limit Upper 16 Bits .......................................................... 87 Offset 34h: CAPP—Capabilities List Pointer ..............................................................................
PAGE 9
Contents 100 101 102 103 Offset 178h: PREFCTRL—Prefetch Control Register ..............................................................119 Offset 300h: PWRBGT_HDR—Power Budgeting Enhanced Capability Header......................120 Offset 304h: PWRBGT_DSEL—Power Budgeting Data Select Register .................................120 Offset 308h: PWRBGT_DATA—Power Budgeting Data Register............................................
PAGE 10
Contents Revision History Date Revision Description May 2005 003 Revised Table 1 and Table 9 October 2004 002 Updated PCI Express operation information in Section 1.1 and Table 2 inSection 2.2. Removed L0s state information throughout manual.
PAGE 11
Introduction Introduction 1 The Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge or the 41210) integrates two PCI Express*-to-PCI/PCI-X bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express* port is compatible with the PCI Express* Specification, Revision 1.0a. The two PCI bus interfaces are comparable with the PCI Local Bus Specification, Revision 2.3 and the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b. 1.
PAGE 12
Introduction • Up to two downstream delayed (memory read, I/O read/write and configuration read/write) transactions • • • • • • 1.
PAGE 13
Signal Description Signal Description 2 The “#” symbol at the end of a signal name indicates that the active (asserted) state occurs when the signal is at a low voltage level. When “#” is not present after the signal name, the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: 2.
PAGE 14
Signal Description Table 1.
PAGE 15
Signal Description 2.2 PCI Express* Interface Table 2. PCI Express* Interface Pins Signal I/O REFCLKp/ REFCLKn I Description PCI Express* Reference Clocks: 100 MHz differential clock pair PCI Express* Serial Data Transmit: PCI Express* differential data transmit signals PETp[7:0]/ PETn[7:0] O X8 Mode: All PETp[7:0]/PETn[7:0] are used. X4 Mode: Only PETp[3:0]/PETn[3:0] are used. X1 Mode: Either PETp[0]/PETn[0] is used or PETp[7]/PETn[7] is used.
PAGE 16
Signal Description 2.3 PCI Bus Interface (Two Instances) Each interface is marked by either the letter “A” or “B” to signify the interface. For example, A_AD refers to the AD bus on PCI bus A, and B_AD refers to the AD bus on PCI bus B. For pin names described in the following sections, an “X” in the name indicates either A or B, for the PCI bus A and PCI bus B sides, respectively. For example, “X_PAR” indicates A_PAR on the PCI bus A and B_PAR on the PCI bus B. Table 3.
PAGE 17
Signal Description Table 3. PCI Interface Pins (Sheet 2 of 2) Signal I/O Description Parity Error: PERR# is driven by an external PCI device when it receives data that has a parity error.
PAGE 18
Signal Description 2.4 PCI Bus Interface 64-Bit Extension (Two Interfaces) Table 4. PCI Interface Pins: 64-Bit Extensions Signal I/O Description A_AD[63:32] B_AD[63:32] I/O PCI Address/Data: The AD signals are a multiplexed address and data bus. This bus provides an additional 32 bits to the PCI bus.
PAGE 19
Signal Description 2.6 Interrupt Interface (Two Interfaces) This section lists the interrupt interface signals. There are two sets of interrupt signals for the standard INTA–INTD PCI signals. Table 6. Interrupt Interface Pins Signal I/O A_INTA# A_INTB# A_INTC# A_INTD# B_INTA# B_INTB# B_INTC# B_INTD# Total Description Interrupt Request Bus: The interrupt lines from PCI interrupts INTA#–INTD# can be routed to these interrupt lines.
PAGE 20
Signal Description 2.7 Reset Straps The following signals are used for static configuration. These signals are all sampled on the rising edge of PERST#. Table 7. Reset Strap Pins Signal A_133EN B_133EN I/O I Description PCI-X 133 MHz Enable: The 133EN pin, when high, allows the PCI-X segment to run at 133 MHz when X_PCIXCAP is sampled high. When 133EN is low, the PCI-X segment runs only at 100 MHz when X_PCIXCAP is sampled high. To tie high: Use an approximately 8.2 KΩ resistor to pull to VCC33.
PAGE 21
Signal Description 2.8 SMBus Interface Table 8. SMBus Interface Pins Signal I/O SMBCLK I/OD SMBDAT I/OD Description SMBus Clock: This signal must be pulled to 3.3 V through an 8.2 KΩ resistor. SMBus Data: This signal must be pulled to 3.3 V through an 8.2 KΩ resistor. SMBus Addressing Straps: These straps set the SMBus address for the 41210 Bridge.
PAGE 22
Signal Description 2.9 Miscellaneous Pins Table 9. Miscellaneous Pins Signal CFGRST# I/O Description O Configuration Reset: This signal is asserted low when ever the bridge goes through a fundemental reset (PERST#, RSTIN#, or PCI Express Reset). This signal should be used to indicate when the local initialization methods should be executed. Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more information.
PAGE 23
Signal Description 2.10 Voltage Pins Table 10. Miscellaneous Pins Signal Number Description RCOMP 1 Analog Compensation Pin: RCOMP is the analog compensation pin for PCI. Pull down to ground through a 100 Ω ±1% resistor. VCC 36 1.5 V Core Voltage: 1.5 V ± 5%. VCCAPE 1 VCCAPCI[2:0] 3 VCCBGPE 1 VSSBGPE 1 Analog Band-gap Ground VCCPE 9 1.5 V PCI Express* Voltage: 1.5 V ±3% VCC33 30 3.3 V PCI I/O Voltage: 3.3 V ±5%.
PAGE 24
Signal Description THIS PAGE INTENTIONALLY LEFT BLANK 24 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
PAGE 25
PCI-X Interface 3 PCI-X Interface This section deals with the specifics of the operation and transaction flow details of the PCI interfaces. 3.1 Initialization The Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge or the 41210) is the source bridge for the PCI bus and senses the X_M66EN, X_133EN, and X_PCIXCAP pins to decide the mode and frequency of operation.
PAGE 26
PCI-X Interface In summary: • • • • A_RST# and B_RST# are outputs from the 41210. PCI clocks are actively driven out from the 41210. The 41210 drives X_AD[31:0], X_BE[3:0], and X_PAR low during PCI bus reset. The 41210 drives X_REQ64# low during reset. 3.2 Transactions Supported 3.2.1 PCI Mode Table 13 lists all the transactions supported by the 41210 on the PCI bus. The 41210 supports full 64-bit addressing upstream and downstream and can both generate and accept dual address cycles. Table 13.
PAGE 27
PCI-X Interface 3.2.2 PCI-X Mode Table 14 lists the transactions that the 41210 supports when the PCI interface is in the PCI-X mode. As a master, the 41210 supports the memory write block command for writes that are multiples of cache-line. Table 14.
PAGE 28
PCI-X Interface 3.2.3.2 Delayed All memory read transactions are delayed read transactions. When the 41210 accepts a delayed read request, it samples the address, command, and address parity. This information is entered into the delayed transaction queue. When the 41210 is in PCI-X mode, transactions follow the split transaction model of PCI-X. Read data returned from PCI Express* for an active delayed transaction entry is forwarded to the PCI-X master as a split completion. 3.2.3.
PAGE 29
PCI-X Interface 3.2.5 LOCK Cycles A lock is established when all the following conditions are true: • A PCI Express* device initiates a Memory Read Lock (MRdLk) request to read from a target PCI device. • LOCK# is asserted on the PCI bus. • The target PCI device responds with a TRDY#. The bus is unlocked when the Unlock Message is received on PCI Express*. When the PCI bus is locked, all upstream memory transactions from that bus are retried.
PAGE 30
PCI-X Interface 3.2.6 Decoding In the PCI mode, the 41210 supports only the linear increment address mode for bursting memory transfers (indicated when the lowest two address bits are equal to 0). When either of these address bits is non-zero, the 41210 disconnects the transaction after the first data transfer. The 41210 decodes all PCI cycles with medium DEVSEL# timing. In the PCI-X mode, 41210 always decodes as a Type A target.
PAGE 31
PCI-X Interface of reordering allowed. Retry is not considered an error condition, so there is no error logging or reporting done on a retry. • The 41210 terminates a transaction with retry to an initiator when one of the following conditions is met: — The 41210 receives a new memory read transaction, and the 41210 delayed transaction queue is full. — The 41210 receives a memory read that has already been queued, but has not completed on PCI Express*.
PAGE 32
PCI-X Interface 3.2.7.2 PCI-X Mode Transaction Termination • Initiator Disconnect or Satisfaction of Byte Count As a PCI-X master, the 41210 uses normal termination (initiator disconnect or satisfaction of byte count) if DEVSEL# is returned by the target within six clock cycles after address phase.
PAGE 33
PCI-X Interface • Target Terminations Initiated by the 41210 The 41210 responds with a retry to PCI-X when one of the following conditions is met: — A memory read transaction occurs and the 41210 delayed transaction queue is full. — A LOCK transaction is established from PCI Express*-to-PCI. — A memory write transaction occurs and the 41210 has no free buffer space to accept the write. — A memory write is from a master other than the master that was previously retried (starvation prevention mechanism).
PAGE 34
PCI-X Interface 3.3 PCI-X Protocol Specifics 3.3.1 Attributes Table 16 describes how the 41210 fills in attribute fields where the PCI-to-PCI Bridge Specification, Revision 1.1 allows some implementation flexibility. Table 16. Intel® 41210 Serial to Parallel PCI Bridge Implementation of Requester Attribute Fields Attribute Function ® 3.3.2 No Snoop (NS) The Intel 41210 Serial to Parallel PCI Bridge only forwards this attribute in both directions and does nothing with it internally.
PAGE 35
PCI-X Interface 3.3.4 Split Transactions • Completer attributes are given in Table 17. Table 17. Intel® 41210 Serial to Parallel PCI Bridge Implementation of Completer Attribute Fields Attribute Byte Count Modified (BCM) Function The 41210 does not set this bit.
PAGE 36
PCI-X Interface For controlling the priority level, there is one bit for each of the PCI REQ# inputs and one bit for the internal request input. Bit[7] in the control register is for the bridge, bit[5] is for REQ[5]#, bit[4] is for REQ[4]#, and so on. A value of 1 in a bit position puts the corresponding master in the high-priority group. Figure 1 represents the arbiter scheme with bits[7:0] in the arbiter control register set to “110 0011”.
PAGE 37
Power Management Power Management 4.1 4 Hardware-Controlled Active State Power Management PCI Express* defines a hardware-initiated power management of the PCI Express* Link called active state power management. Under hardware control, the link can be put into a low-power L0s link state or an even lower-power L1 link state. The Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge or the 41210) supports only the PCI Express* active state power management link state L0s.
PAGE 38
Power Management Intel® 41210 Serial to Parallel PCI Bridge Device Power Management 4.4 Each bridge segment supports PCI-PM 1.1 device power management states D0, D3hot, and D3cold. Each function, when programmed to the D3hot state, behaves as follows: • • • • • • • 4.5 The function responds to configuration cycles from PCI Express*. The function initiates and accepts PCI Express* completion transactions. The function does not respond to memory cycles on PCI Express*.
PAGE 39
Power Management To support the PCI Express* power-management event-signaling protocol, the 41210 supports the following messages: • PME_Turn_Off • PME_TO_ACK PME_Turn_Off is used to turn off PME generation from all PCI Express* devices before the system power-manager disconnects the power from the PCI Express* link hierarchy. The 41210 acknowledges the reception of a PME_Turn_Off message with a PME_TO_ACK message to the north device. Refer to the PCI Express* Specification, Revision 1.
PAGE 40
Power Management THIS PAGE INTENTIONALLY LEFT BLANK 40 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
PAGE 41
Addressing 5 Addressing 5.1 Addressable Spaces within the Intel® 41210 Serial to Parallel PCI Bridge Before discussing all the addressing/configuration aspects of the Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge or the 41210), this section provides a brief summary of the addressable spaces within the 41210 PCI Express*-to-PCI Bridges (functions 0 and 2), the corresponding access mechanism, and a description of when they are applicable.
PAGE 42
Addressing 5.2 Secondary PCI Devices Devices on the secondary PCI bus can be configured as private devices and hidden from BIOS and host software. Devices are hidden by inhibiting the assertion of the IDSEL input of the device during configuration cycles. This feature is configured through the BINIT register. Public and private devices are supported according to Table 20. Table 20. Secondary PCI Device Addressing 5.
PAGE 43
Addressing The extended address bits used to access the configuration region above 256 B are all 0s when the access mechanism compatible with the PCI-to-PCI Bridge Specification, Revision 1.1 is used, or when accessing devices on PCI. Note that 41210, when it translates Type 1 configuration transactions from PCI Express*-to-PCI and finds the extended address bits to be non-zero, terminates the transaction with an unsupported request response on PCI Express*.
PAGE 44
Addressing Figure 2. Type 1 to Type 0 Translation (PCI and PCI-X) PCI Express Header Reserved Ext.
PAGE 45
Addressing Instead of having a secondary IDSEL# pin, the 41210 reserves a device number of 0 for itself. The 41210 claims a Type 0 configuration transaction from PCI-X when the Upstream Configuration Enable bit is set in the Bridge Initialization Register (“Offset FCh: BINIT—Bridge Initialization Register” on page 104) and the AD[16] signal of the transaction is asserted (HIGH) during the address phase of the configuration transaction.
PAGE 46
Addressing The base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at address 30h. The top four bits (bits[7:4] of address 1Ch) of the 8-bit field define bits[15:12] of the I/O base address. The bottom four bits (bits[3:0]) read only as 0h to indicate that the 41210 supports 16-bit I/O addressing only. Bits[11:0] of the base address are assumed to be 0, which naturally aligns the base address to a 4 KB boundary.
PAGE 47
Addressing 5.5 Memory Space Access Mechanism The 41210 supports 64 bits of memory addressing on both interfaces. Two memory windows can be setup for forwarding memory transactions from PCI Express*-toPCI. These windows are defined as part of the standard PCI-to-PCI Bridge configuration space. Inverse decoding is used for forwarding transactions from PCI-to-PCI Express*. Refer to Section 5.6, “VGA Addressing” on page 49 to see how memory cycles in the VGA range are handled.
PAGE 48
Addressing 5.5.1 Memory-Mapped I/O Window Software uses the memory-mapped I/O window to map all non-prefetchable (in other words, reads that have side effects, such as reads to FIFOs, or “read-to-clear” status registers) memory space into PCI memory space. The memory-mapped I/O base address register and memory-mapped I/O limit address register define an address range that the bridge uses to determine when to forward memory commands.
PAGE 49
Addressing 5.5.2 Prefetchable Memory Window The prefetchable memory base and address registers, along with their upper 32-bit counterparts, define an additional address range that the 41210 uses to forward accesses. Software maps the prefetchable PCI memory spaces to this window. The 41210 still treats the memory reads in this region as non-prefetchable. The 41210 forwards a memory transaction from PCI Express* to PCI when the address falls within the range.
PAGE 50
Addressing When this bit is cleared, the 41210 forwards transactions addressing the VGA frame buffer memory and VGA I/O registers from PCI Express* to PCI when the defined memory and I/O address ranges enable forwarding. When cleared, accesses to the VGA frame buffer memory are forwarded from PCI to PCI Express* when the defined memory address ranges enable forwarding. However, the master enable bit must still be set.
PAGE 51
Transaction Ordering 6 Transaction Ordering The Intel® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or 41210) follows the producer-consumer model of a standard PCI Express*-to-PCI bridge. Based on this model, the 41210 implements a set of ordering rules in the upstream and downstream directions. The ordering plane covered by these rules spans the transaction domain covered by PCI Express* and either of the two PCI segments.
PAGE 52
Transaction Ordering 6.2 Downstream Transaction Ordering Table 22 lists the combined set of ordering rules in the downstream path of the 41210. Table 22.
PAGE 53
Interrupt Support 7 Interrupt Support The Intel® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or 41210) can generate an in-band interrupt request on PCI Express* for boot devices and for systems that do not support Message Signaled Interrupts (MSI). 7.1 Legacy Interrupt Sharing PCI Express* provides interrupt messages that emulate the legacy wired mechanism. This feature allows I/O devices to signal PCI-style interrupts using a pair of ASSERT and DEASSERT messages.
PAGE 54
Interrupt Support 7.2 Interrupt Routing for Devices behind a Bridge Given the legacy interrupt sharing scheme shown in Table 23, to get the best legacy interrupt performance (by reducing interrupt sharing), adapter boards must select the appropriate INTA#– INTD# input pin to use on each PCI bus segment. The chosen interrupt input also imposes a PCI device number requirement for the interrupt source as shown in Table 24. Table 24.
PAGE 55
System Management Bus Interface System Management Bus Interface 8 The SMBus interface allows the Intel® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or 41210) to serve as a slave device residing on the SMBus for system management functions and provides for full access to the configuration registers in each function. The SMBus implementation has the following characteristics: • Is based on the System Management Bus Specification, Revision 2.
PAGE 56
System Management Bus Interface 8.1 SMBus Commands The 41210 supports six SMBus commands: • Block Write • Block Read • Word Write • Word Read • Byte Write • Byte Read Sequencing these commands initiates accesses to the internal configuration and memory registers. For high reliability, the 41210 also supports the optional packet-error-checking feature (CRC-8) and is enabled or disabled with each transaction.
PAGE 57
System Management Bus Interface 8.2 Initialization Sequence All configuration read and writes are accomplished through SMBus write(s) followed by an SMBus read (for a read command). For configuration access, the SMBus write sequence is used to initialize the following parameters: • Bus number • Device/function number • 12-bit register number (in two separate bytes on SMBus) Each of the parameters above is sent on the SMBus in separate bytes.
PAGE 58
System Management Bus Interface Figure 6. S DWord Configuration Read Protocol (SMBus Block Write/Block Read, PEC Enabled) 11X0_XXX W A Reg Number [7:0] A Cmd = 11010010 PEC A 11X0_XXX W A Cmd = 11010010 A Sr 11X0_XXX R A Byte Count = 5 A PEC N P Data[7:0] A A Bus Number A Device/Function A Reg Number [15:8] A A Data[31:24] A Clock Stretch A P S A Byte Count = 4 Status Data[23:16] A Data[15:8] B3187-01 Figure 7.
PAGE 59
System Management Bus Interface Figure 8. S DWord Configuration Read Protocol (SMBus Block Write/Block Read, PEC Disabled) 11X0_XXX W A Cmd = 11000010 A Byte Count = 4 A Bus Number A Device/Function A Reg Number [15:8] A Reg Number [7:0] Clock Stretch A P S 11X0_XXX W A Cmd = 11000010 A Sr 11X0_XXX R A Byte Count = 5 A Status A Data[31:24] A Data[23:16] A Data[15:8] A Data[7:0] N P B3189-01 Figure 9.
PAGE 60
System Management Bus Interface 8.2.2 Configuration Writes Configuration writes are accomplished through a series of SMBus writes. As with reads, a write sequence is used first to initialize the bus number, device, function, and register number for the configuration access. The writing of this information can be accomplished through any combination of the supported SMBus write commands (Block, Word or Byte). Note: On SMBus, there is no concept of byte enables.
PAGE 61
System Management Bus Interface Figure 11.
PAGE 62
System Management Bus Interface 8.4 SMBus Interface Reset The master has two ways to reset the slave interface state machine in the 41210: • The master holds SCLK low for 25 ms cumulative. “Cumulative” in this case means that all the “low time” for SCLK is counted between the start and stop bit. When this count totals 25 ms before reaching the stop bit, the interface is reset. • The master holds SCLK continuously high for 50 ms.
PAGE 63
Local Initialization 9 Local Initialization The Intel® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or 41210) includes device-specific registers that allow for control of the bridges’s behavior, both internally and externally. Examples of these device-specific registers are the arbiter control register, the prefetch control register, and so on.
PAGE 64
Local Initialization THIS PAGE INTENTIONALLY LEFT BLANK 64 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
PAGE 65
Clock and Reset 10 Clock and Reset 10.1 Clocking The Intel® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or the 41210) always uses the PCI Express* REFCLK as its primary clock input and drives the PCI clock outputs. The clock domains are shown in Table 28: Table 28.
PAGE 66
Clock and Reset 10.2.1 PERST# Reset Mechanism All the voltage sources in the system are tracked by a system component that asserts the PERST# signal only after all the voltages have been stable for some predetermined time. The 41210 receives the PERST# signal as an asynchronous input, meaning that there is no assumed relationship between the assertion or the de-assertion of PERST# and the reference clock. While the PERST# is de-asserted, the 41210 holds all logic in reset.
PAGE 67
Clock and Reset 10.2.4 Software PCI Reset (SBR—Secondary Bus Reset) Commonly referred to as the Secondary Bus Reset (SBR), the software PCI reset is initiated by a write to the bridge control register and resets only the particular PCI segment.
PAGE 68
Clock and Reset THIS PAGE INTENTIONALLY LEFT BLANK 68 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
PAGE 69
Error Handling Error Handling 11 For each interface, the Intel® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or 41210) implements the specified error-logging and escalation actions as per the interface rules. For example, errors encountered on the PCI interface follow the logging and escalation rules of PCI. The error escalation mechanisms implemented by the 41210 can be fully masked.
PAGE 70
Error Handling 11.2.1 Error Types PCI errors are classified into two categories: fatal and non-fatal: • Fatal errors are those that have the potential to cause data corruption. Software must be careful to contain and escalate these errors (when needed). • Non-fatal errors are those that do not cause any data corruption. These errors include driver errors such as master-abort on PCI and target errors such as target-abort. All errors on PCI are uncorrectable and are forwarded to PCI Express* as such.
PAGE 71
Error Handling 11.2.2.2 Split Termination on PCI-X Interface A split-termination error translation occurs when a completion-required transaction receives a “split termination” response when originally mastered on the PCI-X bus, and a “split completion” error message is later received for the original request. Table 30 describes the completion-status translation for PCI-X split-completion terminations.
PAGE 72
Error Handling 11.2.2.3 Split Termination on PCI Express* Interface Table 31 shows the split-completion errors received on the PCI Express* interface and how they translate to PCI-X. Table 31.
PAGE 73
Register Description 12 Register Description This chapter describes the registers of the Intel® 41210 Serial to Parallel PCI Bridge. 12.1 Register Nomenclature and Access Attributes Table 32 describes the nomenclature used for describing bit attributes throughout this chapter. Table 32. Bit Attribute Definitions Mnemonic Note: Attribute RO Read-Only: This bit cannot be altered by software. This bit can be hard-wired to return a fixed value at all times, or it can be set by hardware on an event.
PAGE 74
Register Description 12.2 Configuration Registers The bridge configuration space follows the standard PCI Express*-to-PCI Bridge configuration space format. Refer to the PCI Express*-to-PCI Bridge Specification, Revision 1.0a for details on the format. Each 41210 Bridge contains an identical set of registers as described in this section for its respective PCI segment. Table 33 and Table 34 show the configuration registers of the 41210 and their address byte offset values.
PAGE 75
Register Description Figure 12. Intel® 41210 Serial to Parallel PCI Bridge Capabilities te Ex nd u ig nf o e C ac ed Sp tio ra n 0xFFF Power Budgeting Capability PCI Express Advanced Error Reporting Capability 0x300 0x100 PCI-X Capability PCI-PM 1.
PAGE 76
Register Description Table 33.
PAGE 77
Register Description Table 34.
PAGE 78
Register Description 12.2.1 Offset 00h: ID—Identifiers Contains the vendor and device identifiers for software. Table 35. Offset 00h: ID—Identifiers Bits Type 31:16 RO 15:0 RO Reset A B 0340h 12.2.2 Description 0341h 8086h Device ID (DID): These bits indicate the device number assigned by Intel to the Intel® 41210 Serial to Parallel PCI Bridge. Vendor ID (VID): This 16-bit field indicates that Intel is the vendor.
PAGE 79
Register Description Table 36. Bits Offset 04h: PCICMD—Command Register (Sheet 2 of 2) Type Reset Description Bus Master Enable (BME): This bit controls the ability of the 41210 to issue memory and I/O read/write requests on the PCI Express* interface. 0 = The 41210 does not respond to any memory or I/O transactions on the PCI interface and stops issuing new requests on PCI Express*. 2 RW 0b 1 = The 41210 processes transactions normally.
PAGE 80
Register Description Table 37. Bits Offset 06h: PSTS—Primary Device Status (Sheet 2 of 2) Type Reset Description Signaled Target Abort (STA): This bit is set when a completion packet with Completer Abort (CA) status is generated on PCI Express*. 11 RWC 0b 0 = No error. 1 = Completer Abort (CA) status transmitted on PCI Express* interface 10:9 RO 00b DEVSEL# Timing (DVT): These bits have no meaning on PCI Express*. Fast decode timing is reported.
PAGE 81
Register Description 12.2.5 Offset 09h: CC—Class Code This register contains the class code, sub-class code, and programming interface for the device. Table 39. Offset 09h: CC—Class Code Bits Type Reset 23:16 RO 06h Base Class Code (BCC): The value of 06h indicates that this is a bridge device. 15:8 RO 04h Sub Class Code (SCC): This 8-bit value indicates that this device is a PCI-to-PCI Bridge.
PAGE 82
Register Description 12.2.9 Offset 18h: BNUM—Bus Numbers This register contains the primary, secondary, and maximum subordinate bus number registers. Table 43. Offset 18h: BNUM—Bus Numbers Bits Type Reset 23:16 RW 00h Subordinate Bus Number (SBBN): These bits indicate the highest PCI bus number downstream of this bridge.
PAGE 83
Register Description 12.2.11 Offset 1Ch: IOBL—I/O Base and Limit This register defines the base and limit, aligned to a 4 KB boundary, of the I/O area of the bridge. Accesses from PCI Express* that are within the ranges specified in this register are sent to PCI when the I/O space enable bit is set. Accesses from PCI Express* that are outside the ranges specified result in an Unsupported Request response. Table 45.
PAGE 84
Register Description 12.2.12 Offset 1Eh: SSTS—Secondary Status For the writable bits in this register, writing 1 to the bit clears the bit. Writing 0 to the bit has no effect. Table 46. Offset 1Eh: SSTS—Secondary Status Bits Type Reset Description 15 RWC 0b Detected Parity Error (DPE): This bit is set to 1 whenever the bridge detects an address or data parity error on the PCI bus.
PAGE 85
Register Description 12.2.13 Offset 20h: MBL—Memory Base and Limit Defines the base and limit, aligned to a 1 MB boundary, of the non-prefetchable memory area of the bridge. Accesses from PCI Express* that are within the ranges specified in this register are sent to PCI when the Memory Space Enable bit is set. Accesses from PCI that are outside the ranges specified are forwarded to PCI Express* when the Bus Master Enable bit is set.
PAGE 86
Register Description 12.2.14 Offset 24h: PMBL—Prefetchable Memory Base and Limit This register defines the base and limit, aligned to a 1 MB boundary, of the prefetchable memory area of the bridge. Accesses from PCI Express* that are within the ranges specified in this register are sent to PCI when the Memory Space Enable bit is set. Accesses from PCI that are outside the ranges specified are forwarded to PCI Express* when the Bus Master Enable bit is set.
PAGE 87
Register Description 12.2.16 Offset 2Ch: PMLU32—Prefetchable Memory Limit Upper 32 Bits This register defines the upper 32 bits of the prefetchable address base register. Table 50. Offset 2Ch: PMLU32—Prefetchable Memory Limit Upper 32 Bits Bits Type Reset 31:0 RW 0000 0000h 12.2.17 Description Prefetchable Memory Limit Upper Portion (PMLU): These bits indicate that full 64-bit addressing is supported.
PAGE 88
Register Description 12.2.20 Offset 3Eh: BCTRL—Bridge Control This register provides extensions to the Command Register (“Offset 04h: PCICMD—Command Register” on page 78) that are specific to a bridge. The Bridge Control Register provides many of the same controls for the secondary interface that are provided by the Command Register for the primary interface. Some bits affect operation of both interfaces of the bridge. Table 54.
PAGE 89
Register Description Table 54. Bits Offset 3Eh: BCTRL—Bridge Control (Sheet 2 of 2) Type Reset Description Master Abort Mode (MAM): This bit controls the bridge’s behavior when a master-abort (or unsupported request) occurs on either interface. This bit does not affect the behavior when the bridge forwards a UR completion from PCI Express* to master-abort on PCI-X. 5 RW 0b 0 = Do not report master-aborts.
PAGE 90
Register Description 12.2.21 Offset 40h: BCNF—Bridge Configuration Register The bridge control bits specific to the Intel® 41210 Serial to Parallel PCI Bridge are listed in Table 55. Table 55. Offset 40h: BCNF—Bridge Configuration Register Bits Type Reset 15 RsvdP 0h 14 RW See Table 11 on page 25. Description Preserved PCI Mode (PMODE): This bit determines the mode of operation of the PCI bus.
PAGE 91
Register Description 12.2.22 Offset 42h: MTT—Multi-Transaction Timer This register controls the amount of time that the 41210 arbiter allows for a PCI initiator to perform multiple back-to-back transactions on the PCI bus. The number of clocks programmed in the MTT represents the time slice (measured in PCI clocks) to be allotted to the current agent, after which the arbiter grants the bus to another agent that is requesting it. Table 56.
PAGE 92
Register Description 12.2.26 Offset 46h: EXP_CAP—PCI Express* Capability This register stores the version number of the capability item and other base information contained in the capability structure. Table 60. Offset 46h: EXP_CAP—PCI Express* Capability Bits Type 15:14 RsvdP 00b 13:9 RO 0 0000b 8 RO 0b Slot Implemented: Not relevant for the 41210 7:4 RO 7h Device/Port Type: These bits indicate that the 41210 is a PCI Express* end-point device.
PAGE 93
Register Description 12.2.28 Offset 4Ch: EXP_DCTL—PCI Express* Device Control Register This register stores command bits that control the 41210 behavior on PCI Express*. Table 62.
PAGE 94
Register Description Table 62. Offset 4Ch: EXP_DCTL—PCI Express* Device Control Register (Sheet 2 of 2) Bits Type Default 2 RW 0b Report Fatal Errors: When this bit is set, generation of the ERR_FATAL message is enabled. 1 RW 0b Report NonFatal Errors: When this bit is set, generation of the ERR_NONFATAL message is enabled. 0 RW 0b Report Correctable Errors: When this bit is set, generation of the ERR_CORR message is enabled. 12.2.
PAGE 95
Register Description Table 64. Bits Offset 50h: EXP_LCAP—PCI Express* Link Capabilities Register (Sheet 2 of 2) Type Default Description L0s Exit Latency: The value in these bits is determined by the setting of the Common Clock Configuration bit (bit[6]) in the Link Control Register (Offset 54h: EXP_LCTL—PCI Express* Link Control Register). Note that software can write bit[6] in the Link Control Register to either a 1 or 0 and these bits then change accordingly.
PAGE 96
Register Description 12.2.32 Offset 56h: EXP_LSTS—PCI Express* Link Status Register Table 66. Offset 56h: EXP_LSTS—PCI Express* Link Status Register Bits Type Default 15:13 RsvdZ 000b 12 RO 1b Description Reserved Zero: Software must always write 0 to these bits. Slot Clock Configuration: When the Intel® 41210 Serial to Parallel PCI Bridge is on a PCI Express* connector, this bit indicates whether it is using the same reference clock that is provided at the connector.
PAGE 97
Register Description 12.2.35 Offset 5Eh: MSI_MC—PCI Express* MSI Message Control Table 69. Offset 5Eh: MSI_MC—PCI Express* MSI Message Control Bits Type Reset Description 15:8 RO 00h Reserved 7 RO 1b 64-Bit Address Capable: When set, this bit indicates that the Intel® 41210 Serial to Parallel PCI Bridge is capable of generating a 64-bit message address. (Set by default.) 6:4 RW 000b Multiple Message Enable: Only one message is supported. These bits are R/W for software compatibility.
PAGE 98
Register Description 12.2.39 Offset 6Dh: PM_NXTP—Power Management Next Item Pointer Table 73. Offset 6Dh: PM_NXTP—Power Management Next Item Pointer Bits Type Reset 7:0 RO D8h Description Next Pointer: This field points to the PCI-X capability as the next capability. 12.2.40 Offset 6Eh: PM_PMC—Power Management Capabilities Table 74. Offset 6Eh: PM_PMC—Power Management Capabilities Bits Type Reset Description 15:11 RO 19h PME_Support: PME assertion is supported when in D3hot.
PAGE 99
Register Description 12.2.41 Offset 70h: PM_PMCSR—Power Management Control/Status Register Table 75.
PAGE 100
Register Description 12.2.44 Offset D8h: PX_CAPID—PCI-X Capabilities Identifier This register identifies this item in the capabilities list as a PCI-X register set. Table 78. Offset D8h: PX_CAPID—PCI-X Capabilities Identifier Bits Type Reset 7:0 RO 07h 12.2.45 Description Identifier (ID): These bits indicate that this is a PCI-X capabilities list. Offset D9h: PX_NXTP—PCI-X Next Item Pointer This register indicates where the next item in the capabilities list resides.
PAGE 101
Register Description 12.2.46 Offset DAh: PX_SSTS—PCI-X Secondary Status This is the PCI-X status register for the bridge secondary side. Table 80. Offset DAh: PX_SSTS—PCI-X Secondary Status Bits Type Reset 15:9 RO 00h Description Reserved Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus.
PAGE 102
Register Description 12.2.47 Offset DCh: PX_BSTS—PCI-X Bridge Status This register identifies PCI-X status register for the bridge primary side. Table 81.
PAGE 103
Register Description 12.2.49 Offset E4h: PX_DSTC—PCI-X Downstream Split Transaction Control This register controls the behavior of the 41210 buffers for forwarding split transactions from PCI Express* to the secondary bus. Table 83. Bits Offset E4h: PX_DSTC—PCI-X Downstream Split Transaction Control Type Reset Description 31:16 RW FFFFh Split Transaction Limit (STL): This field is R/W to accommodate diagnostic software that might want to use it.
PAGE 104
Register Description 12.2.50 Offset FCh: BINIT—Bridge Initialization Register Table 84. Offset FCh: BINIT—Bridge Initialization Register Bits Type Reset 31:5 RO 000 0000h Description Reserved Opaque Memory Window Enable: When this bit is set, the Intel® 41210 Serial to Parallel PCI Bridge hard-codes certain address ranges to the secondary segment of each bridge.
PAGE 105
Register Description 12.2.51 Offset 100h: EXPAERR_CAPID—PCI Express* Advanced Error Capability Identifier This register stores the PCI Express* extended capability ID value. Table 85. Offset 100h: EXPAERR_CAPID—PCI Express* Advanced Error Capability Identifier Bits Type Reset 31:20 RO 300h 19:16 RO 1h 15:0 RO 0001h 12.2.52 Description Next PCI Express* Extended Capability Pointer: This field points to the PCI Express* Power Budgeting Capability as the next capability.
PAGE 106
Register Description 12.2.53 Offset 108h: ERRUNC_MSK—PCI Express* Uncorrectable Error Mask This register controls the reporting of individual uncorrectable errors by device to the host bridge via a PCI Express* error message. This register also controls the logging of the header. Refer to the PCI Express* specifications for details of how the mask bits function.
PAGE 107
Register Description 12.2.54 Offset 10Ch: ERRUNC_SEV—PCI Express* Uncorrectable Error Severity This register controls whether an individual uncorrectable error is reported as a fatal error. An uncorrectable error is reported as fatal when the corresponding error bit in this register is set. When the bit is cleared, the corresponding error is considered non-fatal. Table 88.
PAGE 108
Register Description 12.2.55 Offset 110h: ERRCOR_STS—PCI Express* Correctable Error Status This register reports the error status of individual correctable error sources on a PCI Express* device. An individual error status bit set to 1 indicates that a particular error has occurred. Software can clear the error status by writing a 1 to the respective bit. Table 89.
PAGE 109
Register Description 12.2.56 Offset 114h: ERRCOR_MSK—PCI Express* Correctable Error Mask This register controls the reporting of individual correctable errors via ERR_COR message. A masked error (respective bit set in mask register) is not reported to the host bridge by the 41210. There is a mask bit corresponding to every bit in the Correctable Error Status Register (Offset 110h: ERRCOR_STS—PCI Express* Correctable Error Status). Table 90.
PAGE 110
Register Description 12.2.58 Offset 11C–12Bh: HDR_LOG—PCI Express* Transaction Header Log This register is the transaction header log for PCI Express* errors. Table 92.
PAGE 111
Register Description 12.2.59 Offset 12Ch: PCIXERRUNC_STS—Uncorrectable PCI-X Status Register Table 93. Offset 12Ch: PCIXERRUNC_STS—Uncorrectable PCI-X Status Register (Sheet 1 of 2) Bits Type Reset 15:14 RsvdZ 00b Reserved Zero: Software must write 0 to these bits. 13 RWCS 0b Internal Bridge Data Error: This bit is set when an error occurs in the internal data queues in the Intel® 41210 Serial to Parallel PCI Bridge in either direction. The 41210 does not log any headers for this error.
PAGE 112
Register Description Table 93. Bits 112 Offset 12Ch: PCIXERRUNC_STS—Uncorrectable PCI-X Status Register (Sheet 2 of 2) Type Reset Description 2 RWCS 0b PCI-X Detected Target Abort (optional in specification): The 41210 sets this bit when it is the master of a request transaction on the PCI bus and it receives a target abort. The 41210 logs the header for that transaction. This bit is also set when the bridge receives a PCI-X Split Completion Message with Target Abort Status.
PAGE 113
Register Description 12.2.60 Offset 130h: PCIXERRUNC_MSK—Uncorrectable PCI-X Error Mask Register This register masks the reporting of PCI-X uncorrectable errors. There is one mask bit per error. Note that the status bits are set in the status register regardless of whether the mask bit is on or off. The mask bit also affects the header log for the PCI-X transaction. When the mask bit is on, the header is not logged and no error message is generated on PCI Express*. Table 94.
PAGE 114
Register Description Table 94.
PAGE 115
Register Description 12.2.61 Offset 134h: PCIXERRUNC_SEV—Uncorrectable PCI-X Error Severity Register This register controls the severity of the reporting of PCI-X uncorrectable errors. There is one mask bit per error. When a bit is set to 1, the corresponding error, when enabled, generates an ERR_FATAL message on PCI Express*. When a bit is cleared to 0, the corresponding error, when enabled, causes a ERR_NONFATAL on PCI Express*. Table 95.
PAGE 116
Register Description Table 95. Offset 130h: PCIXERRUNC_SEV—Uncorrectable PCI-X Error Severity Register (Sheet 2 of 2) Bits Type Reset 2 RWCS 0b Description PCI-X Detected Target Abort Severity: (optional in specification) 0 = ERR_NONFATAL 1 = ERR_FATAL PCI-X Detected Split Completion Master Abort Severity: 1 RWCS 0b 0 = ERR_NONFATAL 1 = ERR_FATAL PCI-X Detected Split Completion Target Abort Severity: (optional in specification) 0 RWCS 0b 0 = ERR_NONFATAL 1 = ERR_FATAL 12.2.
PAGE 117
Register Description 12.2.63 Offset 13C–14Bh: PCIXHDR_LOG—Uncorrectable PCI-X Error Transaction Header Log This register is the transaction header log for PCI errors. The log in this register corresponds to one of the status bits set in the PCI-X uncorrectable status register. As soon as an error is logged in this register, it remains locked for further error logging until the software clears the status bit that caused the header log (in other words, the error pointer is re-armed to log again). Table 97.
PAGE 118
Register Description 12.2.65 Offset 170h: SSR—Strap Status Register This register indicates the status of various reset straps in the 41210. Table 99. Offset 170h: SSR—Strap Status Register Bits Type Reset 15 RO Strap 14:8 RO 00h Description Configuration Retry Strap: This bit captures the CFGRETRY strap value at the rising edge of PERST#. Reserved: Read only SMBus Address (SA): These seven bits represent the address to which the SMBus slave port responds when an access is attempted.
PAGE 119
Register Description 12.2.66 Offset 178h: PREFCTRL—Prefetch Control Register The following register contains prefetch parameters for PCI operation. Table 100. Offset 178h: PREFCTRL—Prefetch Control Register Bits Type Reset 63:60 RsvdP 0000b Description Preserved Prefetch Policy (PP): These bits control how the bridge prefetches data on behalf of PCI masters: • 00 = Allow prefetching on MRM, MRL, and MR. 55:54 RW 01b • 01 = Allow prefetching on MRM and MRL, but not on memory read.
PAGE 120
Register Description 12.2.67 Offset 300h: PWRBGT_CAPID—Power Budgeting Enhanced Capability Header This register defines the capability identifier. Table 101. Offset 300h: PWRBGT_HDR—Power Budgeting Enhanced Capability Header Bits Type Reset 31:20 RO 000h 19:16 RO 1h 15:0 RO 0004h Description Next PCI Express* Extended Capability Pointer: This field indicates the last capability.