Datasheet

6 Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Datasheet
Tables
2-1 Itanium
®
Processor System Bus Signal Groups......................................................16
2-2 Nominal Resistance Values for Tuner1, Tuner2, and Tuner3.....................................17
2-3 Processor Package Specifications .........................................................................18
2-4 AGTL+ Signals DC Specifications..........................................................................19
2-5 Power Good Signal DC Specifications....................................................................19
2-6 System Bus Clock Differential HSTL DC Specifications.............................................19
2-7 TAP Connection DC Specifications ........................................................................19
2-8 SMBus DC Specifications.....................................................................................20
2-9 LVTTL Signal DC Specifications............................................................................20
2-10 System Bus Clock Differential HSTL AC Specifications.............................................20
2-11 SMBus AC Specifications.....................................................................................21
2-12 Dual-Core Intel
®
Itanium
®
Processor Absolute Maximum Ratings.............................22
2-13 Source Synchronous AGTL+ Signal Group and Wired-OR Signal Group
Absolute Overshoot/Undershoot Tolerance ............................................................25
2-14 Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 400-MHz System Bus .....................................................26
2-15 Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 400-MHz System Bus......................................26
2-16 Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 533-MHz System Bus .....................................................26
2-17 Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 533-MHz System Bus......................................27
2-18 VR Connector Signals.........................................................................................27
2-19 Power Connector Pinouts ....................................................................................28
2-20 Processors Core Voltage Identification Code (VCORE and VCACHE)...........................30
2-21 Connection for Unused Pins.................................................................................33
2-22 TUNER1/TUNER3 Translation Table.......................................................................34
3-1 Pin/Signal Information Sorted by Pin Name ...........................................................36
3-2 Pin/Signal Information Sorted by Pin Location........................................................50
4-1 Processor Package Dimensions ............................................................................67
4-2 Processor Package Mechanical Interface Dimensions...............................................68
4-3 Processor Package Load Limits at Power Tab .........................................................71
5-1 Case Temperature Specification...........................................................................77
6-1 System Management Interface Signal Descriptions.................................................79
6-2 Thermal Sensing Device SMBus Addressing on the Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 series.............................................................81
6-3 EEPROM SMBus Addressing on the Dual-Core Intel
®
Itanium
®
Processor
9000 and 9100 Series ........................................................................................82
6-4 Processor Information ROM Format ......................................................................82
6-5 Current Address Read SMBus Packet ....................................................................85
6-6 Random Address Read SMBus Packet ...................................................................86
6-7 Byte Write SMBus Packet....................................................................................86
6-8 Write Byte SMBus Packet....................................................................................87
6-9 Read Byte SMBus Packet ....................................................................................87
6-10 Send Byte SMBus Packet ....................................................................................87
6-11 Receive Byte SMBus Packet.................................................................................87
6-12 ARA SMBus Packet.............................................................................................87
6-13 Command Byte Bit Assignment............................................................................88
6-14 Thermal Sensing Device Status Register ...............................................................89
6-15 Thermal Sensing Device Configuration Register......................................................89
6-16 Thermal Sensing Device Conversion Rate Register..................................................90