Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9050 Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9040 Dual-Core Intel® Itanium® Processor 1.6 GHz with 8 MB L3 Cache 9030 Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9020 Dual-Core Intel® Itanium® Processor 1.4 GHz with 12 MB L3 Cache 9015 Intel® Itanium® Processor 1.6 GHz with 6 MB L3 Cache 9010 Dual-Core Intel® Itanium® Processor 1.66/1.
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Contents 1 Introduction............................................................................................................... 11 1.1 Overview ......................................................................................................... 11 1.2 Processor Abstraction Layer ................................................................................ 11 1.3 Mixing Processors of Different Frequencies and Cache Sizes .................................... 12 1.4 Terminology ................
6.4 6.5 6.6 6.7 Processor Information ROM and Scratch EEPROM Supported SMBus Transactions .....................................................................................................85 Thermal Sensing Device .....................................................................................86 Thermal Sensing Device Supported SMBus Transactions..........................................87 Thermal Sensing Device Registers........................................................................88 6.
A.2 A.1.45 LOCK# (I/O)........................................................................................ 100 A.1.46 NMI (I) ............................................................................................... 101 A.1.47 OWN# (I/O) ........................................................................................ 101 A.1.48 PMI# (I) ............................................................................................. 101 A.1.49 PWRGOOD (I) .....................................
Tables 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 3-1 3-2 4-1 4-2 4-3 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6 Itanium® Processor System Bus Signal Groups ......................................................16 Nominal Resistance Values for Tuner1, Tuner2, and Tuner3 .....................................17 Processor Package Specifications .........................................................................
A-1 A-2 A-3 A-5 A-4 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 Address Space Size ........................................................................................... 92 Effective Memory Type Signal Encoding ................................................................ 92 Special Transaction Encoding on Byte Enables ....................................................... 93 BR0# (I/O), BR1#, BR2#, BR3# Signals for 2P Rotating Interconnect ......................
Revision History 8 Document Number Revision Number 314054 -002 314054 -001 Description • Updated with 9100 series product information; updated brand name from “Itanium 2” to “Itanium”. • Initial release of the document.
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9050 Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9040 Dual-Core Intel® Itanium® Processor 1.6 GHz with 8 MB L3 Cache 9030 Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9020 Dual-Core Intel® Itanium® Processor 1.4 GHz with 12 MB L3 Cache 9015 Intel® Itanium® Processor 1.6 GHz with 6 MB L3 Cache 9010 Dual-Core Intel® Itanium® Processor 1.
The Dual-Core Intel® Itanium® processor 9000 and 9100 series delivers new levels of flexibility, reliability, performance, and cost-effective scalability for your most data-intensive business and technical applications. With double the performance of previous Intel Itanium processors, the DualCore Intel Itanium processor 9000 and 9100 series provides more reasons than ever to migrate your business-critical applications off RISC and mainframe systems and onto cost-effective Intel architecture servers.
Introduction 1 Introduction 1.1 Overview The Dual-Core Intel Itanium processor 9000 and 9100 series employs Explicitly Parallel Instruction Computing (EPIC) design concepts for a tighter coupling between hardware and software. In this design style, the interface between hardware and software is engineered to enable the software to exploit all available compile-time information and efficiently deliver this information to the hardware.
Introduction The System Abstraction Layer (SAL) firmware contains platform-specific firmware to initialize the platform, boot to an operating system, and provide runtime functionality. Further information about SAL is available in the Intel® Itanium® Processor Family System Abstraction Layer Specification. 1.
Introduction 1.
Introduction 14 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical specifications of the Dual-Core Intel Itanium Processor 9000 and 9100 series. 2.1 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series System Bus Most Dual-Core Intel Itanium processor 9000 and 9100 series signals use the Itanium processor’s assisted gunning transceiver logic (AGTL+) signaling technology.
Electrical Specifications .. Table 2-1.
Electrical Specifications 2.2.2 Signal Descriptions Appendix A, “Signals Reference”, contains functional descriptions of all system bus signals and LVTTL power pod signals. Further descriptions of the system management signals are contained in Chapter 6. The signals listed under the “Power” and “Other” group are described here: VCTERM System bus termination voltage. GND System ground. N/C No connection can be made to these pins.
Electrical Specifications 2.3 Package Specifications Table 2-3 through Table 2-9 list the DC voltage, current, and power specifications for the processor. The voltage and current specifications are defined at the processor pins. Operational specifications listed in Table 2-3 through Table 2-9 are only valid while meeting specifications for case temperature, clock frequency, and input voltages. Table 2-3.
Electrical Specifications Table 2-4. AGTL+ Signals DC Specifications Symbol Parameter Core Frequency Minimum Typ Maximum Unit Notes 0.625 V 1 V 1 2 VIL Input Low Voltage All VIH Input High Voltage All VOL Output Low Voltage All VOH Output High Voltage All VCTERM, minimum IOL Output Low Current @ 0.3 V All 34 mA 3 IOL Output Low Current @ 0.3 V All 17 mA 4 IL Leakage Current All ±100 µA 5 CAGTL+ AGTL+ Pad Capacitance All 2 pF 6 0.875 0.3 0.
Electrical Specifications Table 2-8. SMBus DC Specifications Parameter Minimum Typ Maximum Unit Notes 3.3V Symbol VCC for the System Management Components 3.14 3.3 3.47 V 3.3 V ±5 VIL Input Low Voltage –0.3 0.3*3.3 V V VIH Input High Voltage 2.31 3.47 V VOL Output Low Voltage I3.3V 3.3V Supply Current IOL Output Low Current IOL2 Output Low Current ILI Input Leakage Current 10 µA ILO Output Leakage Current 10 µA 5.0 Max = 3.3 +5% Min + 0.7*3.3V 0.4 V 30.
Electrical Specifications Table 2-10.System Bus Clock Differential HSTL AC Specifications (Sheet 2 of 2) Symbol Parameter System Bus Clock (MHz) Minimum Typ Maximum Unit Figure Notes Trise BCLKp Rise Time7 All 333 500 667 ps Figure 2-1 20–80% Tfall BCLKp Fall Time7 All 333 500 667 ps Figure 2-1 20–80% VPP Minimum Input Swing All mV Figure 2-1 6 600 Notes: 1. The system clock skew is ±100 ps. 2. Measured on cross-point of rising edge of BCLKp and falling edge of BCLKn.
Electrical Specifications Figure 2-2. SMSC Clock Waveform Thigh Trise SMSC Vcc (3.3V) 90% Vcc 75% Vcc 25% Vcc Tfall Trise = Rise Time Thigh = High Time Tfall = Fall Time Tlow = Low Time Tlow 000618 2.4.1 Maximum Ratings Table 2-12 contains the processor stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating conditions are given in the DC tables.
Electrical Specifications 2.5 System Bus Signal Quality Specifications and Measurement Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal VCTERM voltage (or below GND), as shown in Table 2-3. The overshoot/ undershoot specifications limit transitions beyond VCTERM or GND due to the fast signal edge rates.
Electrical Specifications 2.5.2 Overshoot/Undershoot Pulse Duration Pulse duration describes the total time that an overshoot/undershoot event exceeds the overshoot/undershoot reference voltage (VCTERM/GND). The total time could encompass several oscillations above the reference voltage. Multiple overshoot/ undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration.
Electrical Specifications 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications. 6. Undershoot events must be analyzed separately from overshoot events, as they are mutually exclusive. 2.5.
Electrical Specifications Table 2-14. Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/ Undershoot Tolerance for 400-MHz System Bus Absolute Maximum (V) Pulse Duration (ns) Overshoot Undershoot AF = 11 AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01 1.65 –0.45 0.0035 0.0036 0.0037 0.0040 0.0121 0.0241 0.1207 1.6 –0.4 0.0039 0.0040 0.0045 0.0157 0.0396 0.0799 0.3996 1.55 –0.35 0.0124 0.0168 0.0255 0.0520 0.1309 0.2626 1.3107 1.5 –0.3 0.0405 0.
Electrical Specifications Table 2-16. Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/ Undershoot Tolerance for 533-MHz System Bus (Sheet 2 of 2) Absolute Maximum (V) 1.4 –0.2 Pulse Duration (ns) 0.9925 1.3358 1.875 1.875 1.875 1.875 1.875 1.35 –0.15 1.875 1.875 1.875 1.875 1.875 1.875 1.875 1.3 –0.10 1.875 1.875 1.875 1.875 1.875 1.875 1.875 Notes: 1. Activity Factor = 1 means signal toggles every 3.75 ns. Table 2-17.
Electrical Specifications Figure 2-4. Processors Power Tab Physical Layout 001356 Table 2-19.
Electrical Specifications Table 2-19.
Electrical Specifications Table 2-20. Processors Core Voltage Identification Code (VCORE and VCACHE) Processor Pins (0 = low, 1 = high) 30 400 200 100 50 25 12.5 (mV) 400 200 100 50 25 12.5 (mV) VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 Vout (V) VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 Vout (V) 1 1 1 1 1 1 OFF 0 1 1 1 1 1 1 1 1 1 0 1.3 0 1 1 1 1 0 0.9 1 1 1 1 0 1 1.2875 0 1 1 1 0 1 0.8875 1 1 1 1 0 0 1.275 0 1 1 1 0 0 0.
Electrical Specifications 2.7 System Bus Clock and Processor Clocking The BCLKn and BCLKp inputs control the operating frequency of the processor system bus interface. All processor system bus timing parameters are specified with respect to the falling edge of BCLKn and rising edge of BCLKp. The address pins A[21:17]# will be used to specify the system bus frequency during reset. The processor will ensure that the correct bus/core ratio is elected based on the bus frequency that is specified during reset.
Electrical Specifications Warm Reset Sequence: • PWRGOOD remains high throughout the entire sequence, as power is already available and stable to the processor. • The configuration pins (A[21:17]#) must be asserted the entire time RESET# is asserted. • The duration from the assertion of RESET# to the deassertion of RESET# must be 1 millisecond minimum. • After RESET# is deasserted, the configuration pins must remain valid for two BCLKs (minimum) to three BCLKs (maximum).
Electrical Specifications 2.8 Recommended Connections for Unused Pins Pins that are unused in an application environment (as opposed to testing environment) should be connected to the states listed in Table 2-21. Pins that must be used in an application are stated as such and do not have a recommended state for unused connection. Table 2-21.
Electrical Specifications Table 2-22. TUNER1/TUNER3 Translation Table A[21:17}#1 TUNER12 TUNER32 System Bus (MHz) Slew Rate (V/ns) 0 0 0 667 1.7 0 0 1 533 1.4 0 1 N/A 400 0.8 1 0 0 667 1.92 1 0 1 533 1.7 1 1 N/A 400 0.82 Notes: 1. 0 = VCTERM, 1 = GND 2.
Pinout Specifications 3 Pinout Specifications This chapter describes the Dual-Core Intel Itanium processor 9000 and 9100 series signals and pinout. Note: The pins labeled “N/C” must remain unconnected. The processor uses a JEDEC standard pin naming convention. In this chapter, pin names are the actual names given to each physical pin of the processor. System bus signal names are the names associated with the functions of those pins.
Pinout Specifications Table 3-1 provides the Dual-Core Intel Itanium processor 9000 and 9100 series pin list in alphabetical order. Table 3-2 provides the Dual-Core Intel Itanium processor 9000 and 9100 series pin list by pin location. Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 1 of 15) Pin Name System Bus Signal Name Pin Location 3.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1.
Pinout Specifications Table 3-1. Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Pinout Specifications Table 3-2.
Mechanical Specifications 4 Mechanical Specifications This chapter provides the mechanical specifications of the Dual-Core Intel Itanium processor 9000 and 9100 series. 4.1 Processor Package Dimensions Figure 4-1 through Figure 4-5 provide package mechanical drawings and dimensions of the processor. Table 4-1 and Table 4-2 provide additional details on the package dimensions. The main components of processor package are identified in Figure 4-2. All specified package dimensions are in millimeters.
Mechanical Specifications Figure 4-1.
Mechanical Specifications Table 4-1. Processor Package Dimensions Figure 4-2.
Mechanical Specifications Table 4-2.
Mechanical Specifications Figure 4-3.
Mechanical Specifications Figure 4-4. Processor Package Top-Side Components Height Dimensions Note: Figure 4-5. Processor Package Bottom-Side Components Height Dimensions Note: 70 Keepout zones indicate no components will be on the processor package. Keepout zones indicate no components will be on the processor package.
Mechanical Specifications 4.1.1 Voltage Regulator (MVR) to Processor Package Interface Critical package mechanical requirements at its interface with the MVR are identified in Figure 4-6 and Table 4-3. The processor interface boundary conditions with which MVR must comply during and after installation are outlined in Table 4-3. These requirements are intended to minimize potential damage to the processor that may result from installation of the MVR. Figure 4-6.
Mechanical Specifications Table 4-3. Processor Package Load Limits at Power Tab (Sheet 2 of 2) Parameter Description Value1 Tx Allowable torque at the package power tab in X axis 0.57Nm max T+y Allowable torque at the package power tab in +y direction 1.24 Nm max Allowable torque at the package power tab in -y direction 0.93Nm max T-y Comments Torque on the package edge in +Y direction is determined by the load applied in -Z and the distance from the edge the package to the socket.
Mechanical Specifications Figure 4-7. Processor Top-Side Marking on IHS 4.2.2 Processor Bottom-Side Marking The processor bottom-side mark for the product is a laser marking on the pin side of the interposer. Figure 4-8 shows the placement of the laser marking on the pin side of interposer.
Mechanical Specifications Figure 4-8.
Thermal Specifications 5 Thermal Specifications This chapter provides a description of the thermal features relating to the Dual-Core Intel Itanium processor 9000 and 9100 series. 5.1 Thermal Features The processor has an internal thermal circuit which senses when a certain temperature is reached on the processor core. This circuit is used for controlling various thermal states. In addition, an on-chip thermal diode is available for use by the thermal sensing device on the processor.
Thermal Specifications 5.1.2 Enhanced Thermal Management ETM is a power and thermal protection feature. On the Dual-Core Intel Itanium processor 9000 and 9100 series, ETM uses power and thermal sensing devices on the die to monitor entry points, indicating dangerous operation exceeding the thermal or power specification.
Thermal Specifications Table 5-1. Case Temperature Specification Symbol Tcase Parameter Case Temperature Core Frequency Minimum Maximum Unit 1.6GHz/24MB 5 76 °C 1.6GHz/18MB 5 76 °C 1.6GHz/9MB 5 76 °C 1.42GHz/12MB 5 76 °C 1.4GHz/12MB 5 76 °C 1.6GHz/6MB 5 74 °C Notes Figure 5-2 contains dimensions for the thermocouple location on the processor package. This is the recommended location for placement of a thermocouple for case temperature measurement. Figure 5-2.
Thermal Specifications 78 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
System Management Feature Specifications 6 System Management Feature Specifications The Dual-Core Intel Itanium processor 9000 and 9100 series includes a system management bus (SMBus) interface. This chapter describes the features of the SMBus and SMBus components. 6.1 System Management Bus 6.1.1 System Management Bus Interface The processor includes an Itanium processor family SMBus interface which allows access to several processor features.
System Management Feature Specifications Figure 6-1. Logical Schematic of SMBus Circuitry Intel® Itanium ® 2 Processor 3.3V Core 10K 10K THERMDA 10K VCC THERMDC A0 A1 A2 Processor SC Information SD ROM VCC A0 A1 STBY Thermal Sensing Device SC SD 10K ALERT VCC A0 A1 10K A2 SC Scratch EEPROM SD WP 10K SMA0 3.3V SMWP SMA1 SMA2 SMSD SMSC THRMALERT# 3.3V 3.3V 10K Stuffing Options System Board NOTE: 1. Actual implementation may vary. 2.
System Management Feature Specifications 6.1.3 SMBus Device Addressing Of the addresses broadcast across the SMBus, the memory components claim those of the form “1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the processor at adjacent addresses. The Y bit is hard-wired on the processor to GND (‘0’) for the Scratch EEPROM and pulled to 3.3 V (‘1’) for the processor information ROM. The “XX” bits are defined by the processor socket via the SMA0 and SMA1 pins on the processor connector.
System Management Feature Specifications Table 6-3.
System Management Feature Specifications Table 6-4. Processor Information ROM Format (Sheet 2 of 3) Offset/ Section # of Bits Function Notes Examples 0Bh 16 Reserved Reserved for future use 0000h 0Dh 8 Checksum 1 byte checksum Add up by byte and take 2’s complement.
System Management Feature Specifications Table 6-4.
System Management Feature Specifications Notes: 1. Refer to the Intel® Itanium™ Architecture Software Developer’s Manual for details on CPUID registers. 2. The translation is using BCD. 3. Itanium 9000 and 9100 series use a hex-to-decimal conversion 6.3 Scratch EEPROM Also available on the SMBus interface on the processor is an EEPROM which may be used for other data at the system vendor’s discretion (Intel will not be using the scratch EEPROM).
System Management Feature Specifications Table 6-6. Table 6-7. 6.
System Management Feature Specifications 6.6 Thermal Sensing Device Supported SMBus Transactions The thermal sensing device responds to five of the SMBus packet types: write byte, read byte, send byte, receive byte, and alert response address (ARA). The send byte packet is used for sending one-shot commands only. The receive byte packet accesses the register commanded by the last read byte packet.
System Management Feature Specifications Table 6-13. Command Byte Bit Assignment Command Reset State RESERVED Register 00h N/A Reserved for future use. Function RRT 01h N/A Read processor core thermal data. RS 02h N/A RC 03h 0000 0000 Read configuration byte. Read status byte (flags, busy signal). RCR 04h 0000 0010 Read conversion rate byte. RESERVED 05h 0111 1111 Reserved for future use. RESERVED 06h 1100 1001 Reserved for future use.
System Management Feature Specifications 6.7.2 Thermal Limit Registers The thermal sensing device has two thermal limit registers; they define high and low limits for the processor core thermal diode. The encoding for these registers is the same as for the thermal reference registers. If the diode thermal value equals or exceeds one of its limits, then its alarm bit in the status register is triggered. This indication is also brought out to the processor system bus via the THRMALERT# signal. 6.7.
System Management Feature Specifications 6.7.5 Conversion Rate Register The contents of the conversion rate register determine the nominal rate at which analog-to-digital conversions happen when the thermal sensing device is in autoconvert mode. Table 6-16 shows the mapping between conversion rate register values and the conversion rate. As indicated in Table 6-16, the conversion rate register is set to its default state of 02h (0.25 Hz nominally) when the thermal sensing device is powered-up.
Signals Reference A Signals Reference This appendix provides an alphabetical listing of all Dual-Core Intel Itanium 9000 and 9100 series processor system bus signals. The tables at the end of this appendix summarize the signals by direction: output, input, and I/O. For a complete pinout listing including processor specific pins, please refer to Chapter 3, “Pinout Specifications.” A.1 Alphabetical Signals Reference A.1.
Signals Reference Table A-1. Address Space Size ASZ[1:0]# Memory Address Space Memory Access Range 0 0 Reserved Reserved 0 1 36-bit 0 to (64 GByte - 1) 1 0 50-bit 64 GByte to (1 Pbyte –1) 1 1 Reserved Reserved Any memory access transaction addressing a memory region that is less than 64 GB (that is, Aa[49:36]# are all zeroes) must set ASZ[1:0]# to 01.
Signals Reference For memory or I/O transactions, the byte-enable signals indicate that valid data is requested or being transferred on the corresponding byte on the 128-bit data bus. BE[0]# indicates that the least significant byte is valid, and BE[7]# indicates that the most significant byte is valid. Since BE[7:0]# specifies the validity of only 8 bytes on the 16 byte wide bus, A[3]# is used to determine which half of the data bus is validated by BE[7:0]#.
Signals Reference A.1.10 BINIT# (I/O) If enabled by configuration, the Bus Initialization (BINIT#) signal is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted, all bus state machines are reset. All agents reset their rotating IDs for bus arbitration to the same state as that after reset, and internal count information is lost. The L2 and L3 caches are not affected.
Signals Reference Table A-4. Table A-5.
Signals Reference A symmetric agent can deassert BREQn# before it becomes a symmetric owner. A symmetric agent can reassert BREQn# after keeping it deasserted for one clock. A.1.16 CCL# (I/O) CCL# is the Cache Cleanse signal. It is driven on the second clock of the Request Phase on the EXF[2]#/Ab[5]# pin. CCL# is asserted for Memory Write transaction to indicate that a modified line in a processor may be written to memory without being invalidated in its caches. A.1.
Signals Reference A.1.24 DEN# (I/O) The Defer Enable (DEN#) signal is driven on the bus on the second clock of the Request Phase on the Ab[4]# pin. DEN# is asserted to indicate that the transaction can be deferred by the responding agent. A.1.25 DEP[15:0]# (I/O) The Data Bus ECC Protection (DEP[15:0]#) signals provide optional ECC protection for Data Bus (D[127:0]#). They are driven by the agent responsible for driving D[127:0]#.
Signals Reference A.1.27 DPS# (I/O) The Deferred Phase Enable (DPS#) signal is driven to the bus on the second clock of the Request Phase on the Ab[3]# pin. DPS# is asserted if a requesting agent supports transaction completion using the Deferred Phase. A requesting agent that supports the Deferred Phase will always assert DPS#. A requesting agent that does not support the Deferred Phase will always deassert DPS#. A.1.
Signals Reference A.1.33 FCL# (I/O) The Flush Cache Line (FCL#) signal is driven to the bus on the second clock of the Request Phase on the A[6]# pin. FCL# is asserted to indicate that the memory transaction is initiated by the global Flush Cache (FC) instruction. A.1.34 FERR# (O) The FERR# signal may be asserted to indicate a processor detected error when IERR mode is enabled. If IERR mode is disabled, the FERR# signal will not be asserted in the processor system environment. A.1.
Signals Reference A.1.41 INT (I) INT is the 8259-compatible Interrupt Request signal which indicates that an external interrupt has been generated. The interrupt is maskable. The processor vectors to the interrupt handler after the current instruction execution has been completed. An interrupt acknowledge transaction is generated by the processor to obtain the interrupt vector from the interrupt controller.
Signals Reference A.1.46 NMI (I) The NMI signal is the Non-maskable Interrupt signal. Asserting NMI causes an interrupt with an internally supplied vector value of 2. An external interrupt-acknowledge transaction is not generated. If NMI is asserted during the execution of an NMI service routine, it remains pending and is recognized after the EOI is executed by the NMI service routine. At most, one assertion of NMI is held pending. NMI is rising-edge sensitive.
Signals Reference Table A-10. Transaction Types Defined by REQa#/REQb# Signals Transaction A.1.
Signals Reference A.1.53 RS[2:0]# (I) The Response Status (RS[2:0]#) signals are driven by the responding agent (the agent responsible for completion of the transaction). A.1.54 RSP# (I) The Response Parity (RSP#) signal is driven by the responding agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection.
Signals Reference Table A-11. STBp[7:0]# and STBn[7:0]# Associations A.1.
Signals Reference A.1.67 TRDY# (I) The Target Ready (TRDY#) signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. A.1.68 TRST# (I) The TAP Reset (TRST#) signal is an IEEE 1149.1 compliant TAP support signal used by debug tools. A.1.69 WSNP# (I/O) The Write Snoop (WSNP#) signal indicates that snooping agents will snoop the memory write transaction A.
Signals Reference Table A-13.
Signals Reference Table A-14. Input/Output Signals (Single Driver) (Sheet 2 of 2) Name Active Level Clock Signal Group Qualified REQ[5:0]# Low BCLKp Request ADS#, ADS#+1 ADS#, ADS#+1 RP# Low BCLKp Request SBSY# Low BCLKp Data Always SPLCK# Low BCLKp System Bus ADS#+1 STBn[7:0]# Low — Data Always STBp[7:0]# Low — Data Always WSNP# Low BCLKp System Bus ADS# Clock Signal Group Qualified Table A-15.
Signals Reference 108 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
