MultiProcessor Specification Version 1.
THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. A license is hereby granted to copy and reproduce this specification for internal use only. No other license, express or implied, by estoppel or otherwise, to any other intellectual property rights is granted herein.
Revision History Revision -001 Revision History Date Pre-release Version 1.0. Formerly called “PC+MP Specification” 10/27/93 Version 1.1. Resolves conflicts with MCA-based systems. The following changes have been made: 4/11/94 1. Two MP feature information bytes were moved from the BIOS System Configuration Table to the RESERVED area of the MP Floating Pointer Structure. 2.
Table of Contents Chapter 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Goals ........................................................................................................ 1-1 Features of the Specification .................................................................... 1-2 Scope........................................................................................................ 1-2 Target Audience .......................................................................................
Contents 3.7 3.8 3.9 3.6.6 APIC Identification ..................................................................... 3-13 3.6.7 APIC Interval Timers.................................................................. 3-13 3.6.8 Multiple I/O APIC Configurations ............................................... 3-13 RESET Support ...................................................................................... 3-14 3.7.1 System-wide RESET .................................................................
Contents Appendix A System BIOS Programming Guidelines A.1 A.2 A.3 A.4 BIOS Post Initialization ............................................................................A-1 Controlling the Application Processors ....................................................A-2 Programming the APIC for Virtual Wire Mode .........................................A-2 Constructing the MP Configuration Table................................................A-4 Appendix B Operating System Programming Guidelines B.1 B.
Contents Figures 1-1. 1-2. 2-1. 2-2. 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. 4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 4-7. 4-8. 4-9. 4-10. 4-11. 4-12. 5-1. 5-2. Conceptual Overview ...................................................................... 1-1 Memory Layout Conventions .......................................................... 1-4 Multiprocessor System Architecture................................................ 2-2 APIC Configuration .........................................................................
Contents 4-6. 4-7. 4-8. 4-9. 4-10. 4-11. 4-12. 4-13. 4-14. 4-15. 4-16. 4-17. 5-1. 5-2. 5-3. D-1. Feature Flags from CPUID Instruction ............................................ 4-9 Bus Entry Fields ............................................................................ 4-10 Bus Type String Values................................................................. 4-11 I/O APIC Entry Fields .................................................................... 4-12 I/O Interrupt Entry Fields ............
1 Introduction The MultiProcessor Specification, hereafter known as the “MP specification,” defines an enhancement to the standard to which PC manufacturers design DOS-compatible systems. MP-capable operating systems will be able to run without special customization on multiprocessor systems that comply with this specification. End users who purchase a compliant multiprocessor system will be able to run their choice of operating systems.
MultiProcessor Specification 1.2 Features of the Specification The MP specification includes the following features: • • • • • • • A multiprocessor extension to the PC/AT platform that runs all existing uniprocessor shrinkwrapped binaries, as well as MP binaries. Support for symmetric multiprocessing with one or more processors that are Intel architecture instruction set compatible, such as the CPUs in the Intel486™ and the Pentium® processor family.
Introduction In addition to the hardware requirements, this document also specifies MP features that are visible to the BIOS and operating system. However, it is important to understand that as hardware technology progresses, the functions performed by the BIOS may change in accordance with the hardware technology. ONLY THE INTERFACE TO THE OPERATING SYSTEM LEVEL IS EXPECTED TO REMAIN CONSTANT. This specification does not address issues relating to the processor's System Management Mode (SMM). 1.
MultiProcessor Specification 1.6 Conventions Used in This Document Signal names that are followed by the character # represent active low signals. For example, FERR# is active when at its low-voltage state. Throughout this document, the Intel 82489DX APIC is referred to as the “discrete APIC.” The term “integrated APIC” is used to refer to an APIC integrated with other system components, such as the Pentium 735\90 and 815\100 processors.
2 System Overview In the realm of multiprocessor architectures, there are several conceptual models for tying together computing elements, and there are a variety of interconnection schemes and details of implementation. Figure 2-1 shows the general structure of a design based on the MP specification. The MP specification’s model of multiprocessor systems incorporates a tightly-coupled, sharedmemory architecture with a distributed interprocessor and I/O interrupt capability.
MultiProcessor Specification CPU CPU CPU HIGH-BANDWIDTH MEMORY BUS ICC BUS SHARED MEMORY MODULE GRAPHICS FRAME BUFFER APIC APIC I/O INTERFACE I/O INTERFACE I/O EXPANSION BUS I/O EXPANSION BUS APIC ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER ICC INTERRUPT CONTROLLER COMMUNICATIONS Figure 2-1. Multiprocessor System Architecture 2.1 Hardware Overview The MP specification defines a system architecture based on the following hardware components: • • • • 2.1.
System Overview only during the initialization and shutdown processes. The BSP is responsible for initializing the system and for booting the operating system; APs are activated only after the operating system is up and running. CPU1 is designated as the BSP. CPU2, CPU3, and so on, are designated as the APs.
MultiProcessor Specification The local APIC units also provide interprocessor interrupts (IPIs), which allow any processor to interrupt any other processor or set of processors. There are several types of IPIs. Among them, the INIT IPI and the STARTUP IPI are specifically designed for system startup and shutdown. Each local APIC has a Local Unit ID Register and each I/O APIC has an I/O Unit ID Register. The ID serves as a physical name for each APIC unit.
System Overview 2.2 BIOS Overview A BIOS functions as an insulator between the hardware on one hand, and the operating system and applications software on the other. A standard uniprocessor BIOS performs the following functions: • • • • Tests system components. Builds configuration tables to be used by the operating system. Initializes the processor and the rest of the system to a known state. Provides run-time device-oriented services.
3 Hardware Specification This section outlines the minimal set of common hardware features necessary for the operating system to operate on multiple hardware platforms. The MP hardware specification defines how the components mentioned in Chapter 2 are implemented.
MultiProcessor Specification 4GB FFFF_FFFFH BIOS PROM FFFE_0000H FEF0_0000H LOCAL APIC FEE0_0000H FED0_0000H I/O APIC FEC0_0000H MEMORY-MAPPED I/O SPACE EXTENDED MEMORY REGION 1MB 0010_0000H SHADOWED BIOS 000F_0000H 000E_0000H SHADOWED EXPANSION BIOS EXPANSION ROM 000D_0000H ROM EXTENSIONS 000C_0000H VIDEO BUFFER 640K 000A_0000H SYSTEM-BASED MEMORY 0000_0000H PART OF THIS SPECIFICATION UNSHADED ADDRESS REGIONS ARE FOR REFERENCE ONLY AND SHOULD NOT BE CONSTRUED AS THE SOLE DEFINITION OF A PC/AT
Hardware Specification Table 3-1. Memory Cacheability Map Addresses (in hex) Size Description Shared by All Processors? Cacheable? Comment 0000_0000h – 0009_FFFFh 640KB Main memory Yes Yes 000A_0000h – 000B_FFFFh 128KB Display buffer for video adapters Yes No 000C_0000h – 000D_FFFFh 128KB ROM BIOS for add-on Yes cards Yes 000E_0000h – 000F_FFFFh 128KB System ROM BIOS Yes Yes Yes Maximum address depends on total memory installed in the system.
MultiProcessor Specification 3.3 External Cache Subsystem Intel-compatible processors support multiprocessing both on the processor bus and on a memory bus, both with and without secondary cache units. Due to the high bandwidth demands of multiprocessor systems, external caches are often employed to improve performance. The existence and implementation details of external caches are not a part of this specification.
Hardware Specification operations over its internal shared memory bus, if it is AT compatible. Operating system and software developers must ensure that data is aligned if locked access is required, because lock operations on misaligned data are not guaranteed to work on all platforms. 3.5 Posted Memory Write When controlling I/O devices, it is important that memory and I/O operations be carried out in the order programmed.
MultiProcessor Specification Table 3-2. APIC Versions APIC Type Local APIC Version Register (hexadecimal) 82489DX APIC 0x Integrated APIC, i.e., Pentium processors (735\90, 815\100) 1x Integrated APIC Features STARTUP IPI. See Appendix B.4.2 for details. Programmable interrupt input polarity NOTE: x is a 4-bit hexadecimal number. To encourage future extendibility and innovation, the Intel APIC architecture definition is limited to the programming interface of the APIC units.
Hardware Specification The first two interrupt modes, PIC Mode and Virtual Wire Mode, provide PC/AT-compatibility. At least one of these modes must be implemented in systems that comply with the MP specification. In these modes, full DOS compatibility with the uniprocessor PC/AT is provided by using the APICs in conjunction with standard 8259A-equivalent programmable interrupt controllers (PICs). The third mode, Symmetric I/O Mode, must be implemented in addition to either PIC Mode or Virtual Wire Mode.
MultiProcessor Specification BSP AP1 AP2 CPU 1 CPU 2 CPU 3 IMCR E0 REG. MARK NMI INTR NMI INTR LOCAL APIC 1 LINTIN0 LINTIN1 NMI INTR LOCAL APIC 2 LINTIN0 LINTIN1 LOCAL APIC 3 LINTIN0 LINTIN1 LINTIN1 LINTIN0 RESET ICC BUS NMI 8259AEQUIVALENT PICS INTR I/O APIC INTERRUPT INPUTS SHADED AREAS INDICATE UNUSED CIRCUITS. DOTTED LINE SHOWS INTERRUPT PATH. Figure 3-2.
Hardware Specification 3.6.2.2 Virtual Wire Mode Virtual Wire Mode provides a uniprocessor hardware environment capable of booting and running all DOS shrink-wrapped software. In Virtual Wire Mode, as shown in Figure 3-3, the 8259A-equivalent PIC fields all interrupts, and the local APIC of the BSP becomes a virtual wire, which delivers interrupts from the PIC to the BSP via the local APIC’s local interrupt 0 (LINTIN0).
MultiProcessor Specification Figure 3-3 shows how Virtual Wire Mode can be implemented through the BSP’s local APIC. It is also permissible to program the I/O APIC for Virtual Wire Mode, as shown in Figure 3-4. In this case the interrupt signal passes through both the I/O APIC and the BSP’s local APIC. BSP AP1 AP2 CPU 1 CPU 2 CPU 3 NMI INTR REG.
Hardware Specification 3.6.2.3 Symmetric I/O Mode Some MP operating systems operate in Symmetric I/O Mode. This mode requires at least one I/O APIC to operate. In this mode, I/O interrupts are generated by the I/O APIC. All 8259 interrupt lines are either masked or work together with the I/O APIC in a mixed mode. See Figure 3-5 for an overview of Symmetric I/O Mode. BSP AP1 AP2 CPU 1 CPU 2 CPU 3 NMI INTR REG.
MultiProcessor Specification 3.6.3 Assignment of System Interrupts to the APIC Local Unit The APIC local unit has two general-purpose interrupt inputs, which are reserved for system interrupts. These interrupt inputs can be individually programmed to different operating modes. Like the I/O APIC interrupt lines, the local APIC interrupt line assignments of a non-PC/ATcompatible system are system implementation specific.
Hardware Specification 3.6.6 APIC Identification Systems developers must assign APIC local unit IDs and ensure that all are unique. There are two acceptable ways to assign local APIC IDs, as follows: • • By hardware. The ID of each APIC local unit is sampled from the appropriate pins at RESET. By the BIOS. Software can override the APIC IDs assigned by hardware by writing to the Local Unit ID Register.
MultiProcessor Specification REG. MARK INTR/LINT0 ICC BUS NON-ISA INTERRUPT I/O APIC 2 INTERRUPT ROUTING NETWORK ISA INTERRUPT I/O APIC 1 8259AEQUIVALENT PICS Figure 3-6. Multiple I/O APIC Configurations 3.7 RESET Support To bring all circuitry in a computer system to an initial state, computer systems require a systemwide reset capability.
Hardware Specification or by the front panel reset button (if the system is so equipped). This type of reset operates without regard to cycle boundaries, and, for example, is connected to the RESET pin of Pentium processors. 3.7.2 System-wide INIT The system-wide INIT, as defined by this specification, refers to a soft or warm reset that initializes only portions of the processor.
MultiProcessor Specification 3.8 System Initial State The system initial state is the state before the BIOS gives control to the operating system. It is identical to the system initial state of a typical PC/AT system, with the additional MP components in the following state: 1. All local APICs are disabled, except for the local APIC of the BSP if the system starts in Virtual Wire Mode. 2. All pending I/O APIC interrupts are cleared and disabled. 3.
4 MP Configuration Table The operating system must have access to some information about the multiprocessor configuration. The MP specification provides two methods for passing this information to the operating system: a minimal method for configurations that conform to one of a set of common hardware defaults, and a maximal method that provides the utmost flexibility in hardware design. Figure 4-1 shows the general layout of the MP configuration data structures.
MultiProcessor Specification The following two data structures are used: 1. The MP Floating Pointer Structure. This structure contains a physical address pointer to the MP configuration table and other MP feature information bytes. When present, this structure indicates that the system conforms to the MP specification. This structure must be stored in at least one of the following memory locations, because the operating system searches for the MP floating pointer structure in the order described below: a.
MP Configuration Table 4.1 MP Floating Pointer Structure An MP-compliant system must implement the MP floating pointer structure, which is a variable length data structure in multiples of 16 bytes. Currently, only one 16-byte data structure is defined. It must span a minimum of 16 contiguous bytes, beginning on a 16-byte boundary, and it must be located within the physical address as specified in the previous section.
MultiProcessor Specification Table 4-1. MP Floating Pointer Structure Fields (continued) Field Offset Length (in bytes:bits) (in bits) Description MP FEATURE INFORMATION BYTE 1 11 8 Bits 0-7: MP System Configuration Type. When these bits are all zeros, the MP configuration table is present. When nonzero, the value indicates which default configuration (as defined in Chapter 5) is implemented by the system. MP FEATURE INFORMATION BYTE 2 12:0 12:7 7 1 Bits 0-6: Reserved for future MP definitions.
MP Configuration Table 4.2 MP Configuration Table Header Figure 4-3 shows the format of the header of the MP configuration table, and Table 4-2 explains each of the fields.
MultiProcessor Specification Table 4-2. MP Configuration Table Header Fields 4.3 Field Offset Length (in bytes) (in bits) Description SIGNATURE 0 32 The ASCII string representation of “PCMP,” which confirms the presence of the table. BASE TABLE LENGTH 4 16 The length of the base configuration table in bytes, including the header, starting from offset 0. This field aids in calculation of the checksum. SPEC_REV 6 8 The version number of the MP specification. A value of 01h indicates Version 1.
MP Configuration Table Table 4-3. Base MP Configuration Table Entry Types Entry Description Entry Type Code* Length (in bytes) Comments Processor 0 20 One entry per processor. Bus 1 8 One entry per bus. I/O APIC 2 8 One entry per I/O APIC. I/O Interrupt Assignment 3 8 One entry per bus interrupt source. Local Interrupt Assignment 4 8 One entry per system interrupt source. * All other type codes are reserved. 4.3.
MultiProcessor Specification Table 4-4. Processor Entry Fields Field Offset Length (in bytes:bits) (in bits) Description ENTRY TYPE 0 8 A value of 0 identifies a processor entry. LOCAL APIC ID 1 8 The local APIC ID number for the particular processor. LOCAL APIC VERSION # 2 8 Bits 0–7 of the local APIC’s version register. CPU FLAGS: EN 3:0 1 If zero, this processor is unusable, and the operating system should not attempt to access this processor.
MP Configuration Table Table 4-5. Intel486 and Pentium Processor Signatures a Family Model Stepping Description 0000 0000 0000 Not a valid CPU signature.
MultiProcessor Specification 4.3.2 Bus Entries Bus entries identify the kinds of buses in the system. Because there may be more than one bus in a system, each bus is assigned a unique bus ID number by the BIOS. The bus ID number is used by the operating system to associate interrupt lines with specific buses. Figure 4-5 shows the format of a bus entry, and Table 4-7 explains the fields of each entry.
MP Configuration Table Table 4-8. Bus Type String Values Bus Type String Description CBUS Corollary CBus CBUSII Corollary CBUS II EISA Extended ISA FUTURE IEEE FutureBus INTERN Internal bus ISA Industry Standard Architecture MBI Multibus I MBII Multibus II MCA Micro Channel Architecture MPI MPI MPSA MPSA NUBUS Apple Macintosh NuBus PCI Peripheral Component Interconnect PCMCIA PC Memory Card International Assoc.
MultiProcessor Specification 4.3.3 I/O APIC Entries The configuration table contains one or more entries for I/O APICs. Figure 4-6 shows the format of each I/O APIC entry, and Table 4-9 explains each field. 31 24 23 16 15 8 7 0 04H MEMORY-MAPPED ADDRESS OF I/O APIC I/O APIC FLAGS E RESERVED N 31 I/O APIC VERSION # 24 23 ENTRY TYPE 2 I/O APIC ID 16 15 8 7 00H 0 Figure 4-6. I/O APIC Entry Table 4-9.
MP Configuration Table 2. No Interrupt Assignment Entries are declared for any of the bus source interrupts, and the operating system uses some other bus-specific knowledge of bus interrupt schemes in order to support the bus. This operating system bus-specific knowledge is beyond the scope of this specification.
MultiProcessor Specification Table 4-10. I/O Interrupt Entry Fields 4-14 Field Offset (in bytes:bits) Length (in bits) ENTRY TYPE 0 8 Entry type 3 identifies an I/O interrupt entry. INTERRUPT TYPE 1 8 See Table 4-11 for values. PO 2:0 2 Polarity of APIC I/O input signals: 00 = Conforms to specifications of bus (for example, EISA is activelow for level-triggered interrupts) 01 = Active high 10 = Reserved 11 = Active low Must be 00 if the 82489DX is used.
MP Configuration Table Table 4-11. Interrupt Type Values Interrupt Type* Description Comments 0 INT Signal is a vectored interrupt; vector is supplied by APIC redirection table. 1 NMI Signal is a nonmaskable interrupt. 2 SMI Signal is a system management interrupt. 3 ExtINT Signal is a vectored interrupt; vector is supplied by external PIC. For example, if an 8259 is used as the external PIC, the source is the 8259 INTR output line, and the vector is supplied by the 8259.
MultiProcessor Specification Table 4-12. Local Interrupt Entry Fields 4-16 Field Offset (in bytes:bits) Length (in bits) Description ENTRY TYPE 0 8 Entry type 4 identifies a local interrupt entry. INTERRUPT TYPE 1 8 See Table 4-11 for values PO 2:0 2 Polarity of APIC local input signals: 00 = Conforms to specifications of bus (for example, EISA is active-low for level triggered interrupts) 01 = Active high 10 = Reserved 11 = Active low Must be 00 if the 82489DX is used.
MP Configuration Table 4.4 Extended MP Configuration Table Entries A variable number of variable-length entries are located in memory, immediately following entries in the base section of the MP configuration table described in Section 4.3. These entries compose the extended section of the MP configuration table.
MultiProcessor Specification 4.4.1 System Address Space Mapping Entries System Address Space Mapping entries define the system addresses that are visible on a particular bus. Each bus defined in the Base Table can have any number of System Address Space Mapping entries included in the Extended Table. Thus, individual buses can be configured to support different address ranges, thereby decreasing the amount of bus traffic on a given bus and increasing the overall system performance.
MP Configuration Table Table 4-14. System Address Space Mapping Entry Fields Field Offset (in bytes:bits) Length (in bits) ENTRY TYPE 0 8 Entry type 128 identifies a System Address Space Mapping Entry. ENTRY LENGTH 1 8 A value of 20 indicates that an entry of this type is twenty bytes long. BUS ID 2 8 The BUS ID for the bus where the system address space is mapped. This number corresponds to the BUS ID as defined in the base table bus entry for this bus.
MultiProcessor Specification Figure 4-10. Example System with Multiple Bus Types and Bridge Types Since all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices (i.e., ISA, EISA) should support all possible addresses to that bus.
MP Configuration Table 4.4.2 Bus Hierarchy Descriptor Entry If present, Bus Hierarchy Descriptor entries define how I/O buses are connected relative to each other in a system with more than one I/O bus. Bus Hierarchy Descriptors are used to supplement System Address Mapping entries to describe how addresses propagate to particular buses in systems where address decoding cannot be completely described by System Address Space Mapping entries alone.
MultiProcessor Specification Table 4-15 Bus Hierarchy Descriptor Entry Fields Field Offset (in bytes:bits) Length (in bits) ENTRY TYPE 0 8 Entry type 129 identifies a Bus Hierarchy Descriptor Entry. ENTRY LENGTH 1 8 A value of 8 indicates that this entry type is eight bytes long. BUS ID 2 8 The BUS ID identity of this bus. This number corresponds to the BUS ID as defined in the base table bus entry for this bus. BUS INFORMATION:SD 3:0 1 Subtractive Decode Bus.
MP Configuration Table For example, a host bus bridge for a PCI bus that provides ISA compatibility may decode a predefined range of addresses used for ISA device support in addition to the addresses used for PCI devices on that bus. A Compatibility Bus Address Space Modifier can be used in this case to add these predefined address ranges to the list specified by System Address Space Mapping entries for that PCI bus.
MultiProcessor Specification Table 4-16. Compatibility Bus Address Space Modifier Entry Fields Field Offset (in bytes:bits) Length (in bits) ENTRY TYPE 0 8 Entry type 130 identifies a Compatibility Bus Address Space Modifier Entry. ENTRY LENGTH 1 8 A value of 8 indicates that an entry of this type is eight bytes long. BUS ID 2 8 Bus for address space mappings are to be modified. This number corresponds to the BUS ID as defined in the base table entry for this bus.
5 Default Configurations The MP specification defines several default MP system configurations. The purpose of these defaults is to simplify BIOS design. If a system conforms to one of the default configurations, the BIOS will not need to provide the MP configuration table. The operating system will have the default MP configuration table predefined internally. Default system configuration types are defined by MP feature information byte 1, which is part of the MP floating pointer structure.
MultiProcessor Specification Table 5-1. Default Configurations Default Number Config Code of CPUs Bus Type APIC Type 1 2 ISA 82489DX 2 2 EISA 82489DX 3 2 EISA 82489DX As in Figure 5-1. 4 2 MCA 82489DX As in Figure 5-1, but without EISA bus logic, with inverters before I/O APIC inputs 1-15. 5 2 ISA + PCI Integrated As in Figure 5-2, but without EISA logic. 6 2 EISA + PCI Integrated As in Figure 5-2.
Default Configurations BSP AP2 INTEL486 CPU 1 INTEL486 CPU 3 NMI INTR RESET NMI INTR RESET A IMCR E0 PNMI PINT PRST ExtINTA LOCAL 82489DX APIC REG.
MultiProcessor Specification The INTA TRAP and GLUE in the figure are the additional hardware interface logic needed for the 82489DX APIC. INTA TRAP conditions all interrupt acknowledge cycles with ExtINTA to steer the vector either from the 8259A PIC or the APIC. INTA TRAP is also responsible for preventing the interrupt acknowledge cycle from reaching the 8259A PIC, in case ExtINTA is negated when PINT is activated. During an interrupt acknowledge cycle with ExtINTA active, the APIC does not return RDY#.
Default Configurations BSP AP PENTIUM (735\90, 815\100) CPU2 PENTIIUM (735\90, 815\100) CPU1 LOCAL APIC APICEN LOCAL APIC APICEN REG.
MultiProcessor Specification should be cross-connected between the BSP and AP processors. Although the INIT pin is crossconnected between BSP and AP, a targeted INIT IPI initializes only the targeted processor, because the INIT IPI does not cause the INIT pin to change state. The interconnection of I/O APIC interrupt lines is the same as for the 82489DX APIC configuration.
Default Configurations Certain EISA chipsets do not bring out the IRQ0, 8254 timer interrupt, and IRQ13 EISA DMA chaining interrupt signals. If these signals are not directly available, INTIN2 and INTIN13 should be disabled. Refer to Section 5.3.1 for more details. 5.3.1 EISA and IRQ13 IRQ13 is a shared interrupt as defined in the EISA bus specification. Because a compliant system supports only the on-chip floating point unit, IRQ13 carries only the EISA chaining interrupt.
MultiProcessor Specification The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software. In PIC-Mode configurations, the NMI signal is delivered to the local interrupt input 1 (LINTIN1) of all local APICs and the input of a 2-to-1 MUX. When the system is operated in PIC Mode, the NMI is sent to the BSP directly via the MUX.
A System BIOS Programming Guidelines Depending on the MP components in a multiprocessor system, the system BIOS may have the following additional responsibilities: 1. Put the APs to sleep, so that they do not all try to execute the same BIOS code as the BSP. This is necessary, because BIOS code is not typically multithreaded for multiprocessing. 2. Initialize the APICs and other MP components (if any). 3.
MultiProcessor Specification A.2 Controlling the Application Processors Provision must be made to prevent all processors from executing the BIOS after a power-on RESET. System developers may choose to do this by the hardware alone or by cooperation between hardware and the BIOS. In the latter case, the BIOS may be used for selecting the BSP and placing all APs to sleep after POST. The BIOS may use the APIC ID as a means by which to identify each processor and select the proper code sequence to execute.
System BIOS Programming Guidelines ;-----------------------------------------------------------------------; ; InitLocalAPIC( ) ; ;-----------------------------------------------------------------------; ; ; ; Initialize the local APIC to virtual wire mode.
MultiProcessor Specification mov mov and or mov esi,LVT1 eax,[esi] eax,0FFFE00FFH eax,000005700H [esi],eax ; ; ; ; read LVT1 not masked, edge, active high ExtInt write LVT1 ; ; Program LVT2 as NMI, which delivers the signal on the NMI signal of all ; processors' cores listed in the destination.
System BIOS Programming Guidelines The BSP is responsible for positioning the MP configuration table. The table can be located within any unreported, hidden system memory space or within the BIOS ROM region. The BIOS can select any unused space in those regions. For example, some PC/AT systems implement the Extended BIOS Data Segment, a 1-Kbyte block usually positioned at the top of the PC’s 640K base memory.
B Operating System Programming Guidelines The goal of the MP specification is to transfer enough information about the hardware environment to the operating system that a single, shrink-wrapped, operating-system binary can boot-up and fully utilize a wide variety of multiprocessor systems. The following sections explain how the operating system can take advantage of this specification to handle these operations: 1. Operating-system boot-up. 2. Self configuration. 3. Interrupt mode initialization. 4.
MultiProcessor Specification The operating system’s first task is to determine whether the system conforms to the MP specification. This is done by searching for the MP floating pointer structure. If a valid floating pointer structure is detected, it indicates that the system is MP-compliant, and the operating system should continue to look for the MP configuration table.
Operating System Programming Guidelines Then the operating system should enable its own local APIC, thereby allowing IPI communications with other APIC-based processors. At this time, the APs’ local APICs have interrupts disabled. Interrupts must remain disabled at the APs’ local APICs while the BSP is enabling the I/O APIC and bringing the system to the normal operating state. Otherwise, an I/O interrupt may be delivered to the uninitialized AP, resulting in the loss of the interrupt.
MultiProcessor Specification A period of 20 microseconds should be sufficient for IPI dispatch to complete under normal operating conditions. If the IPI is not successfully dispatched, the operating system can abort the command. Alternatively, the operating system can retry the IPI by writing the lower 32-bit double word of the ICR.
Operating System Programming Guidelines By putting an appropriate pointer in the warm-reset vector, setting the shutdown code to 0Ah, then causing an INIT, the BIOS (or the operating system) can cause the current processor to jump immediately to any location. Because all processors in an MP system share the same system memory, and because the INIT IPI gives one processor the power to cause an INIT at another, the operating system can cause any processor to jump immediately to any location. B.4.
MultiProcessor Specification of an INIT IPI used to shut down an AP. As a result, the operating system must ensure that any required state information is captured and that caches are flushed as necessary before sending the INIT IPI. In order to do a complete system shutdown, followed by a warm restart if necessary, the operating system should return the system to a state similar to that at power-on.
Operating System Programming Guidelines interrupt. The distributed APIC architecture, by its nature, is more vulnerable to spurious interrupt, because the device interrupt may be latched and recognized without the INTA cycle. To ensure that spurious interrupts are handled properly, it is strongly recommended that the device drivers must read the status register before servicing the device. In cases where spurious interrupts do occur, the device drivers may simply ignore them.
C System Compliance Checklist Any "NO" answer indicates non-compliance. Condition YES NO 1. PC/AT Compatibility Does system contain all necessary MP-compatible circuitry? Will system boot and run DOS and Microsoft Windows? 2.
D Multiple I/O APIC Multiple PCI Bus Systems The information in this specification describes the majority of multiprocessor systems. This appendix provides clarifications for implementors who are considering designs with more than one I/O APIC. In particular, a number of proposed systems will incorporate multiple I/O APICs in order to support multiple PCI buses. This appendix provides guidance for implementors who wish to be sure that their designs comply with this specification. D.
MultiProcessor Specification If IMCR is implemented but the system includes one or more I/O APICs that are not controlled through IMCR, the hardware must accomplish routing changes for such I/O APICs by some other means when the system switches into symmetric I/O mode. These routing changes must be done without requiring any additional intervention from software.
Multiple I/O APIC Multiple PCI Bus Systems Fixed interrupt routing also implies a restriction on software that is implicit but important in the context of systems with more than one I/O APIC. The operating system must program I/O APICs to handle only the interrupts for which the MP configuration table contains corresponding I/O interrupt assignment entries. If the configuration table contains no entry for a given I/O APIC input, that interrupt must be left in the masked state. D.
E Errata The following sections provided here are intended to replace the corresponding sections in the main body of the specification. The sections provided here are shown in their entirety to provide context for the changes. Changes contained below are marked with double underlined text which shows changes relative to the version of the sections that are provided in the main body of the specification. 4.
MultiProcessor Specification Table 4-1. MP Floating Pointer Structure Fields Field Offset Length (in bytes:bits) (in bits) SIGNATURE 0 32 The ASCII string represented by “_MP_” which serves as a search key for locating the pointer structure. PHYSICAL ADDRESS POINTER 4 32 The address of the beginning of the MP configuration table. All zeros if the MP configuration table does not exist. LENGTH 8 8 The length of the floating pointer structure table in paragraph (16-byte) units.
MP Configuration Table information byte 2, the IMCR present bit, is used by the operating system to determine whether PIC Mode or Virtual Wire Mode is implemented by the system. The physical address pointer field contains the address of the beginning of the MP configuration table. If it is nonzero, the MP configuration table can be accessed at the physical address provided in the pointer structure. This field must be all zeros if the MP configuration table does not exist. 4.4.
MultiProcessor Specification Table 4-14. System Address Space Mapping Entry Fields Field Offset (in bytes:bits) Length (in bits) ENTRY TYPE 0 8 Entry type 128 identifies a System Address Space Mapping Entry. ENTRY LENGTH 1 8 A value of 20 indicates that an entry of this type is twenty bytes long. BUS ID 2 8 The BUS ID for the bus where the system address space is mapped. This number corresponds to the BUS ID as defined in the base table bus entry for this bus.
MP Configuration Table Since all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices (i.e., ISA, EISA) should support all possible addresses to that bus. In general, the MP configuration table must provide entries to describe system address space mappings for all I/O buses present in the system. There are two exceptions to this rule: 1.
MultiProcessor Specification 31 28 27 24 23 20 19 16 15 12 11 8 7 RESERVED BUS INFO RESERVED 31 28 27 S D 24 23 BUS ID 20 19 ENTRY LENGTH 16 15 12 11 8 7 4 3 0 PARENT BUS 04H ENTRY TYPE 129 00H 4 3 0 Figure 4-11. Bus Hierarchy Descriptor Entry Table 4-15 Bus Hierarchy Descriptor Entry Fields Field Offset Length (in bytes:bits) (in bits) ENTRY TYPE 0 8 Entry type 129 identifies a Bus Hierarchy Descriptor Entry.
Glossary 82489DX: The 82489DX Advanced Programmable Interrupt Controller (APIC). 8259A: The 8259A Programmable Interrupt Controller (PIC) or its equivalent. AP: Application processor, one of the processors not responsible for system initialization. APIC: Advanced Programmable Interrupt Controller, either the 82489DX APIC or the integrated APIC on Pentium processors. BIOS: Basic Input/Output Subsystem. BSP: Bootstrap processor, the processor responsible for system initialization.
MultiProcessor Specification PIC Mode: One of three interrupt modes defined by the MP specification. In this mode the APICs are effectively disabled, while interrupts are generated by 8259A-equivalent PICs and delivered directly to the BSP. This is a uniprocessor compatibility mode. POST: Power-On Self Test, the first BIOS procedure executed after a RESET or INIT. RESET: The system-wide hard reset. This definition is functional.
Order Number: 242016-006 Printed in U.S.A.
