Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 99
11.4.1.3 EOI
The EOI is set when CPU initiates a write to address FEE000B0h. Upon receipt of
the EOI write, the MVIC clears the highest-priority ISR bit, which corresponds to
the interrupt that was just serviced. The MVIC ignores the actual value written to
the EOI Register.
0/Ignored
31
0
11.4.1.4 SIVR
SW writes the vector used for spurious interrupts to the SIVR
Reserved
31
8 7
0
Vector
11.4.1.5 ISR
This register tracks interrupts that have already requested service to the core but
have not yet been acknowledged by SW. The MVIC set the bit in ISR (In-Service
Register) after the core recognizers the corresponding interrupt. The bit in the ISR
is cleared when SW writes to the EOI register. Bit N corresponds to the interrupt
request N for interrupt vectors 32 to 63.
31
0
3233
63 62
30
1