Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
98 Document Number: 333577-002EN
11.4.1 MVIC Registers
Table 29 enumerates all the programmable registers in the MVIC:
Table 29: MVIC registers
11.4.1.1 TPR
SW writes to this register with a line number to set a priority threshold. The MVIC
will not deliver unmasked interrupts with line number lower than the TPR value.
Since the vectors are fixed, the TPR is programmed with the corresponding interrupt
line number (0 to 31). Software should NOT program the vector into the TPR
register. The line number to vector mapping is done internal to the MVIC.
If SW programs the TPR as 32, then all un-masked interrupts will not be delivered.
Register Description :
Reserved
31
8 7
0
Line Number
11.4.1.2 PPR
The MVIC sets the PPR to either the highest priority pending interrupt in the ISR or
the current task priority, whichever is higher.
Reserved
31
8 7
0
Line Number
Memory Mapped Address Register Name Access
Description
FEE00080h TPR R/W Task Priority Register
FEE000A0h PPR RO Process Priority Register
FEE000B0h EOI WO End-of-Interrupt Register
FEE000F0h SIVR R/W Spurious Interrupt Vector Register
FEE00110h ISR RO In-Service Register
FEE00210h IRR RO Interrupt Request Register
FEE00320h LVTTIMER R/W Local Vector Table Timer Register
FEE00380h ICR R/W Timer Initial Count Register
FEE00390h CCR RO Timer Current Count Register