Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
96 Document Number: 333577-002EN
Table 27. Mapping Lakemont Bytes Enables to AHB
Lakemont AHB
Byte
Enables
Transfer Size ADDR[1:0] HSIZE[2:0] HADDR[1:0]
0000b No Valid Bytes - - -
0001b 8-bit 00b 000b 00b
0010b 8-bit 01b 000b 01b
0011b 16-bit 00b 001b 00b
0100b 8-bit 10b 000b 10b
0101b
Non-Contiguous Bytes
(Note1)
- - -
0110b
16-bit 01b Not
Supported
Not
Supported
0111b
24-bit 00b Not
Supported
Not
Supported
1000b 8-bit 11b 000b 11b
1001b Non-Contiguous Bytes - - -
1010b Non-Contiguous Bytes - - -
1011b Non-Contiguous Bytes - - -
1100b 16-bit 10b 001b 10b
1101b Non-Contiguous Bytes - - -
1110b
24-bit 01b Not
Supported
Not
Supported
1111b 32-bit 00b 010b 00b
Note1: Processor does not issue transactions with Non-Contiguous Bytes.
AHB Fabric returns all 0’s as data if address is out of bound. On DTCM, when address
does not fall into SRAM region, SRAM controller returns data that is programmable via
a register. Similarly, on ITCM, when address does not fall into Flash Code or OTP Code
regions, Flash controller returns data that is programmable via a register.