Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 95
Intel
®
Quark™ microcontroller D2000 does not assert STPCLK# and hence Stop Grant
Acknowledge cycle is not generated by processor.
11.3.1.6 MSI
The SoC AHB fabric will not send MSIs to the processor so an external interface for
MSIs is not required.
MSIs may be exchanged between the components within integrated MVIC. However,
these MSIs remain internal to the processor sub-system and not no appear on the
AHB fabric.
BLV SoC does not assert NMI pin of LMT.
11.3.1.7 End of Interrupt
The processor subsystem provides an integrated MVIC. There are no other interrupt
controllers in the SoC. As a result, there is no need to signal EOI information to any
agent connected on the AHB fabric.
EOI information may be exchanged between the components within MVIC.
11.3.2 Mapping FSB to AHB
The processor core is a master on the internal SoC AHB fabric and a gasket to convert
from FSB protocol to AHB is provided. The operation of the gasket and the interface to
the AHB fabric is transparent to software.
11.3.2.1 Byte Enables
For read accesses on AHB-Lite interface, Lakemont always asserts all byte enables.
Lakemont does not issue burst reads or writes on AHB-Lite interface. For single writes,
byte enable handling is described in the following paragraphs.
Lakemont allows all combination of byte enables for 32-bit accesses provided that
there is at least one enabled byte and that the enabled bytes are contiguous. This
gives 10 valid 4-bit combinations for the byte enables, allowing 8-, 16-, 24- and 32-
bit transfers.
AHB only allows 8-, 16- and 32-bit transfers in a single beat as specified by HSIZE.
There is no support for 24-bit transfers.
In addition, the AMBA specification states that all transfers within a burst must be
aligned to the address boundary equal to the size of the transfer as specified by
HSIZE. This means that 16-bit transfers must start at 16b address boundary. In
certain cases (unaligned 16b transaction or 24b transactions), processor splits them
into 2 independent transactions on AHB Lite interface. AMBA specification also
requires all transfers be aligned to address boundary equal to the size of the transfer.
As described inTable 27, only 7 combinations are generated by processor on AHB-Lite
interface.