Datasheet
Processor Core
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
94 Document Number: 333577-002EN
If the processor generates a Flush Acknowledge Special cycle, it will be internally
acknowledged to allow the processor to make forward progress but it will not appear
on the AHB fabric or on any other external interface
11.3.1.5.3 Flush Special Cycle
The Flush Special Cycle is generated by an x86 processor when an INVD instruction is
executed.
As the processor does not have an L1 cache, the INVD instruction is not required to be
executed and the Flush Special cycle is not expected to appear on the main fabric bus.
If the code contains an INVD, the processor’s behavior shall be to be to treat this
instruction as a NOP.
11.3.1.5.4 Shutdown Special Cycle
The Shutdown Special Cycle is generated by Lakemont when a triple fault occurs. The
special cycle indicates that the processor has ceased program execution and is in the
shutdown state. The processor must be reset in order to exit the shutdown state.
If the processor generates a Special Cycle, it will be internally acknowledged and an
output on the external interface will be asserted. This signal can be used by an
external system agent to issue a reset to the processor.
In response to Shutdown, Intel
®
Quark™ microcontroller D2000 performs a warm
reset of SoC and cause of reset is logged in a sticky register.
11.3.1.5.5 Halt Special Cycle
The Halt Special Cycle is generated by an x86 processor when a HLT instruction is
executed.
If the processor generates a Halt Cycle, it will be internally acknowledged and an
output on the external interface will be asserted. This signal can be used by an
external system agent to issue take an action for power management or to track the
state of the processor.
When Intel
®
Quark™ microcontroller D2000 detects Halt cycle, it waits for a
programmable number of clocks (>6 clocks) before clock-gating the processor. Any
break event (interrupt or Probe Mode activity via xrsnn interface) restarts the clock.
Clock is not gated if any break event is pending. LMT JTAG activity does not ungate
clock.
11.3.1.5.6 Stop Grant Acknowledge Special Cycle
The Stop Grant Acknowledge Special Cycle is generated by an x86 processor when the
processor enter the Stop Grant state in response to STPCLK# being asserted.
If the processor generates a Stop Grant Acknowledge Special Cycle, it will be
internally acknowledged and an output on the external interface will be asserted. This
signal can be used by an external system agent to issue take an action for power
management or to track the state of the processor.