Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 93
Address on DTCM interface is 18b DW address. Hence, total DTCM address space is
1MB. Lowest 3 address bits are always driven to 0’s by the processor.
Address, issued by LMT, on DTCM, is relative address and starts from offset 0 with
respect to base address of 0x0028_0000. Only 512KB [0x0028_0000 to 0x002F_FFFF]
is mapped to DTCM on LMT.
LMT is an in-order machine with a single instruction in flight. AHB response in the
fabric for a memory write makes the write on AHB-Lite interface posted. Since there is
no L1 cache for processor, all transactions are uncached and hence serialized by
processor.
Processor routes all probe mode accesses towards AHB-Lite.
11.3.1.3 IO Reads and IO Writes
IO reads and writes are under SW control and SW must not issue them. These
requests are aliased into Memory address space on AHB-Lite interface.
11.3.1.4 Interrupt Acknowledge
Interrupt Acknowledge cycles are expected to be completed by the integrated MVIC.
There is no external interrupt controller connected to the AHB fabric that could provide
the interrupt vector information.
11.3.1.5 Special Cycles
The Lakemont processor provides special bus cycles to indicate that certain
instructions have been executed or certain conditions have occurred internally. This
section describes how the Intel
®
Quark™ microcontroller D2000 SoC handles each of
the special cycles.
11.3.1.5.1 Write-Back/Sync Special Cycle
The Writeback Special Cycle is generated by an x86 processor when a WBINVD
instruction is executed.
As the processor does not have an L1 cache, the WBINVD instruction is not required
to be executed and the Writeback Special cycle is not expected to appear on the main
fabric bus interface.
If the code contains a WBINVD, the processor’s behavior shall be to be to treat it as a
NOP.
11.3.1.5.2 Flush Ack Special Cycles
First Flush Acknowledge and Second Flush Acknowledge Special Cycles are generated
by Lakemont-class processor to indicate the completion of a cache flush in response to
the FLUSH# pin being asserted.
As the processor does not have a L1 cache, the FLUSH# pin will not used and Flush
Acknowledge Special Cycles are not expected to appear on the AHB-Lite interface.