Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
92 Document Number: 333577-002EN
11.3 Main Fabric Bus Cycle Processing
The Lakemont CPU supports the following AHB-lite cycles:
• Code Read
• Memory Read (Data)
• Memory Write (Data)
The following sections describe the behavior of the SoC for all these supported types.
11.3.1.1 Code Reads
Code Reads that fall within the I-TCM memory address range will be forwarded to the
I-TCM interface. Code Reads outside of the ITCM range will be forwarded by default to
the AHB-lite fabric, this includes code reads to the DTCM range. Immediate data in
code fetches are also routed to AHB.
Access latency, as seen by the processor, to both Flash Code and OTP Code regions is
the same.
Address on ITCM interface is 19b DW address. Hence, total ITCM address space is
2MB of space. Lowest address bit is always driven to 0 by the processor since ITCM is
64b wide.
Address, issued by LMT, on ITCM is relative address. It starts from offset 0 with
respect to base address of 0x0.
All accesses on ITCM are 8B address aligned and 64b access. There is no burst and no
byte-enables. Hence, processor performs 2 read accesses for every 16B cacheline.
Processor cannot write to ITCM interface (either as probe mode or in any other way).
Protocol on ITCM allows for variable wait-state from Flash.
Processor routes all probe mode accesses towards AHB-Lite.
Attribute HPROT[0] = 0 on AHB-Lite interface indicates Code reads while HPROT[0] =
1 indicates Data accesses.
There is no burst support on AHB interface.
11.3.1.2 Memory Reads and Memory Writes
Memory accesses (data), both read and writes that fall within the D-TCM memory
range will be forwarded to the D-TCM interface. Memory accesses outside of the D-
TCM range will be forward to the AHB-lite fabric.
Memory accesses (data) are not allowed to access the I-TCM. Accesses to that region
will be forward to the AHB-lite fabric.
Processor only issues a single 32b request. All accesses on DTCM are 8B address
aligned and 64b access. Byte Enables indicate which 32b on 64b DTCM is valid – for
both reads and writes.