Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 91
The CPU address map for Intel
®
Quark™ microcontroller D2000 is as follows:
Notes:
• Reset Vector from CPU is mapped to 0x150 and falls into OTP Code region.
• OPEN: In which of the above regions will LMT implement “wrap-around-protect”?
• This is Lakemont Memory view – not Intel
®
Quark™ microcontroller D2000
Memory view.
• N1: LMT routes memory writes to Instruction* regions towards AHB. These writes
are dropped by SoC’s Memory subsystem.
• N2: LMT routes writes to Data ROM region towards AHB. These writes are dropped
by SoC’s Memory subsystem.
• N3: These requests are treated, by SoC, in the same manner (including Access
Control) as normal memory read requests from LMT.
• N4: LMT routes such requests towards AHB. These requests are treated, by SoC,
in the same manner (including Access Control) as normal memory read requests
from LMT.
• Note that OTP Data (Data ROM Memory Type in 1st column of above table) resides
on AHB interface – from Lakemont perspective.
• Code accesses, if any, to DATA SRAM or DATA ROM regions (in 1st column of
above table) are routed to AHB by LMT. Similarly, data accesses, if any, to
Instruction Flash or Instruction RAM or Instruction ROM (in 1st column of above
table) are routed to AHB by LMT.
• Self-modifying code is not supported in Intel
®
Quark™ microcontroller D2000.
o However, if it happens, LMT will route writes to Instruction Flash region
towards AHB. These writes are dropped by SoC’s Memory subsystem. A
following read from LMT will appear on ITCM returning incorrect/previous
value in Flash.
• Intel
®
Quark™ microcontroller D2000 always completes a request on ITCM, DTCM
and AHB interfaces when address is out of bounds or there is an access violation.
• System addresses 0xFFFF_FFF0 and 0xFFFF_FFF8 are a special case by LMT and
get aliased to reset vector.