Datasheet
Introduction
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 9
15.3.1.57 Data Register (DR32) .............................................. 273
15.3.1.58 Data Register (DR33) .............................................. 274
15.3.1.59 Data Register (DR34) .............................................. 275
15.3.1.60 Data Register (DR35) .............................................. 275
15.3.1.61 RX Sample Delay Register (RX_SAMPLE_DLY) ............. 276
16 DMA Controller ............................................................................................. 277
16.1 Features ........................................................................................... 277
16.2 Use .................................................................................................. 277
16.3 Memory Mapped IO Registers ............................................................... 279
16.3.1.1 Channel0 Source Address (SAR0) .............................. 281
16.3.1.2 Channel0 Destination Address (DAR0) ....................... 281
16.3.1.3 Channel0 Linked List Pointer (LLP0) ........................... 282
16.3.1.4 Channel0 Control LOWER (CTL_L0) ........................... 282
16.3.1.5 Channel0 Control UPPER (CTL_U0) ............................ 287
16.3.1.6 Channel0 Source Status (SSTAT0) ............................ 289
16.3.1.7 Channel0 Destination Status (DSTAT0) ...................... 289
16.3.1.8 Channel0 Source Status Address (SSTATAR0) ............. 290
16.3.1.9 Channel0 Destination Status Address (DSTATAR0)....... 290
16.3.1.10 Channel0 Configuration LOWER (CFG_L0) .................. 291
16.3.1.11 Channel0 configuration UPPER (CFG_U0) ................... 293
16.3.1.12 Channel0 Source Gather (SGR0) ............................... 296
16.3.1.13 Channel0 Destination Scatter (DSR0) ........................ 297
16.3.1.14 Channel1 Source Address (SAR1) .............................. 298
16.3.1.15 Channel1 Destination Address (DAR1) ....................... 298
16.3.1.16 Channel1 Linked List Pointer (LLP1) ........................... 299
16.3.1.17 Channel1 Control LOWER (CTL_L1) ........................... 300
16.3.1.18 Channel1 Control UPPER (CTL_U1) ............................ 304
16.3.1.19 Channel1 Source Status (SSTAT1) ............................ 306
16.3.1.20 Channel1 Destination Status (DSTAT1) ...................... 306
16.3.1.21 Channel1 Source Status Address (SSTATAR1) ............. 307
16.3.1.22 Channel1 Destination Status Address (DSTATAR1)....... 307
16.3.1.23 Channel1 Configuration LOWER (CFG_L1) .................. 308
16.3.1.24 Channel1 configuration UPPER (CFG_U1) ................... 310
16.3.1.25 Channel1 Source Gather (SGR1) ............................... 313
16.3.1.26 Channel1 Destination Scatter (DSR1) ........................ 314
16.3.1.27 Raw Status for IntTfr Interrupt (RAW_TFR) ................ 314
16.3.1.28 Raw Status for IntBlock Interrupt (RAW_BLOCK) ......... 315
16.3.1.29 Raw Status for IntSrcTran Interrupt (RAW_SRC_TRAN) 316
16.3.1.30 Raw Status for IntDstTran Interrupt (RAW_DST_TRAN) 316
16.3.1.31 Raw Status for IntErr Interrupt (RAW_ERR) ................ 317
16.3.1.32 Status for IntTfr Interrupt (STATUS_TFR) ................... 318
16.3.1.33 Status for IntBlock Interrupt (STATUS_BLOCK) ........... 318
16.3.1.34 Status for IntSrcTran Interrupt (STATUS_SRC_TRAN) .. 319
16.3.1.35 Status for IntDstTran Interrupt (STATUS_DST_TRAN) .. 319
16.3.1.36 Status for IntErr Interrupt (STATUS_ERR) .................. 320
16.3.1.37 Mask for IntTfr Interrupt (MASK_TFR) ........................ 320
16.3.1.38 Mask for IntBlock Interrupt (MASK_BLOCK) ................ 321
16.3.1.39 Mask for IntSrcTran Interrupt (MASK_SRC_TRAN) ....... 322
Mask for IntDstTran Interrupt (MASK_DST_TRAN) ..................... 323
16.3.1.40 Mask for IntErr Interrupt (MASK_ERR) ....................... 323
16.3.1.41 Clear for IntTfr Interrupt (CLEAR_TFR) ...................... 324
16.3.1.42 Clear for IntBlock Interrupt (CLEAR_BLOCK) ............... 325
16.3.1.43 Clear for IntSrcTran Interrupt (CLEAR_SRC_TRAN) ...... 325
16.3.1.44 Clear for IntDstTran Interrupt (CLEAR_DST_TRAN) ...... 326