Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
88 Document Number: 333577-002EN
11 Processor Core
The SoC provides a single core x86 processor with separate and independent Tightly
Coupled Memory (TCM) Interfaces for Instruction and Data.
Figure 8. Processor Core
Quark
TM
Core
JTAG
Local APIC
I/O APIC
AHB-Lite
Instruction TCM
Data TCM
IOs
32 IRQs
11.1 Features
• Single Processor Core
• Single Instruction 5-stage pipeline
• 32-bit Processor with 32-bit Data Bus
• Native 32b AHB-Lite Interface
• 64b Data TCM Interface to Internal System SRAM
o Data Transfers for addresses matching the Internal System SRAM range
will appear on the Data TCM Interface and transfers to address outside
this range will appear on the AHB-Lite Interface
• 64b Instruction TCM Interface to Internal System Non-Volatile-Memory (NVM)
o Instruction Fetches for addresses matching the Internal NVM range will
appear on the Instruction TCM Interface and transfers to address outside
this range will appear on the AHB-Lite Interface
• Support for IA 32-bit with Pentium x86 ISA compatibility
o Reset Vector of 0x0000_0150
o Little Endian
• Support for CPUID Instruction
• Support for long NOP Instruction
• Time Stamp Counter (TSC) accessed with the RDTSC instruction