Datasheet

Power Up and Reset Sequence

Intel

Quark™ microcontroller D2000

Datasheet January 2016

86 Document Number: 333577-002EN

a. Note that RSTC.WARM register bit gets cleared at WARM_RST#.

Similarly watchdog timer, processor and other interrupt generation

blocks are reset by warm reset.

4. WARM_RST# is released.

Note 1: Following interrupt sources are not to be redirected to trigger warm reset as

they will not get cleared due to warm reset, leading to SoC permanently under warm

reset. Only a power recycle or RST_N recycle will recover this condition.

1. RTC Interrupt (INT_RTC_HOST_HALT_MASK register shall remain masked

permanently – default value)

2. Comparator Interrupt (INT_COMPARATORS_HOST_HALT_MASK[18:0]

3. AON Timer Interrupt (INT_AON_TIMER_HOST_HALT_MASK register shall

remain masked permanently – default value)