Datasheet

Power Up and Reset Sequence
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 85
9.3.2 Cold Reset
A cold reset will trigger a power cycle of the Host domain (Processor Subsystem,
Memory Subsystem, Peripheral Subsystem and Fabric) and trigger a reset of registers
both in the Host and AON (SCSS) domains. There is no reset cycling of most of AON
domain (SCSS) logic and also certain SCSS registers due to a cold reset.
Table 25. Cold Reset Triggers
Trigger Description
Software writes 1 to RSTC.COLD Software Initiated via Reset Control Register
When a cold reset is triggered, the following sequence occurs:
1. A cold reset event is detected.
2. SCSS asserts COLD_RST# and WARM_RST#. Note that POR_RST# is not
asserted; RAR Voltage Regulator is not affected and continues to operate in
same mode as before.
3. Wait for cold reset triggers to get cleared.
a. Note that RSTC.COLD register bit gets cleared at COLD_RST#.
4. COLD_RST# and WARM_RST# are released.
9.3.3 Warm Reset
A warm reset will trigger a reset of all Host domain logic and all non-sticky registers.
There is no power cycling of the Host or AON domains due to a warm reset. Intel
®
Quark™ microcontroller D2000 is single always-on power domain for the entire design
(DVDD).
Table 26. Warm Reset Triggers
Trigger Description
Software writes 1 to RSTC.WARM Software Initiated via Reset Control Register
Watchdog Expires -
Host Halt Interrupt (Redirected to warm
reset)
This is achieved by unmasking
HOST_HALT_MASK register bit of a given
interrupt source along with
P_STS.HALT_INT_REDIR = 0.
Restriction of interrupt sources is given in
Note 1 below.
lmt.shutdown Host processor shutdown. This triggers warm
reset instead of CPU-only reset.
When a warm reset is triggered, the following sequence occurs:
1. A warm reset event is detected.
2. SCSS asserts WARM_RST#. This resets host domain including processor core.
3. Wait for Warm Reset triggers to get cleared.