Datasheet

Power Up and Reset Sequence
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
84 Document Number: 333577-002EN
9.3.1 Power On Reset
The SoC provides an on-die circuitry to provide a power on reset when main power is
applied. The power on reset is asserted when the SoC is powering up and is released
when VCC_AON_1P8 has crossed a given threshold for a certain length of time.
The only mechanism to trigger a power on reset is to remove and then re-apply main
power.
Only indication to SoC that power recycling happened is RST_N input pin. Whenever
there is power recycle, RST_N is expected to be asserted and then de-asserted once
input power rail PVDD is within the operating voltage range [2.0V to 3.6V]. In case of
a power recycle, RST_N has to be kept asserted till DVDD core voltage is also stable
(internal voltage regulator has attained regulation, tROK_PROG < 100 usec). Hence
RST_N is taken as proxy of power-on reset
RST_N could be asserted at other times as well to trigger a complete SoC reset. Only
PVDD power recycle will restart the on-die voltage regulator. RST_N will reset the
entire SoC including System Control Subsystem (SCSS) and registers.
When RST_N is triggered, the following sequence occurs:
1. A RST_N event is detected.
2. SCSS asserts POR_RST#, COLD_RST# and WARM_RST#.
3. Waits till RST_N is deasserted. Then deasserts POR_RST# used by SCSS logic
(PMU, CCU).
4. RAR Voltage Regulator is set to eSR Switching Regulator mode. Ensured by
default value of configuration register (AON_VR.VREG_SEL).
5. The RTC Power Down input is de-asserted. Hybrid Oscillator is enabled in
Silicon Oscillator mode at 4MHz Frequency Select. This is done by default
values of corresponding SCSS registers (OSC0_CFG0/1, OSC1_CFG0) which
are reset at cold reset.
a. This is to ensure that if the cold reset was triggered while in a
Sleeping state with the RTC disabled, the 32 kHz clock and Hybrid Si
Oscillator 4MHz get restarted.
b. The mux select config register (CCU_SYS_CLK_SEL) to choose system
clock is automatically set to select Hybrid Si Oscillator [Intel
®
Quark™
microcontroller D2000 can work without RTC clock].
c. Once the clock is running, the PMU accepts the cold reset request and
asserts both COLD_RST# and WARM_RST#.
6. PMU generates a strobe on VSEL_STROBE to RAR to put it in eSR mode at
1.8V VSEL_IN. Pulse width of VSEL_STROBE is based on
PM_WAIT.VSTRB_WAIT register. At the positive edge of VSEL_STROBE, RAR
deasserts ROK_BUF_VREG (if it is enabled/selected by VR_EN input).
a. When RAR is power recycled, RAR will default to eSR 1.8V mode
automatically. However at other times of RST_N, RAR may be in other
mode (for example, qLR Linear Regulator and non 1.8V). Hence this
strobing is done by PMU to get it predictably back to eSR 1.8V
regulation mode.
7. PMU waits for ROK_BUF_VREG from RAR to be asserted so that voltage
regulator (VR) has attained regulation. In case RAR VR is bypassed by VR_EN
input pin, RAR VR keeps ROK_BUF_VREG asserted always.
8. COLD_RST# and WARM_RST# are released.