Datasheet
Power Up and Reset Sequence
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 83
9.2.2 Power Sequence Analog Characteristics
The following table describes the analog characteristics of the blocks used in the SoC
power sequences.
Table 24. Power Sequence Analog Characteristics
Parameter Minimum Typical Maximum Units
Time taken to attain
regulation (from EN=0 to
1) eSR t
ON
0.15 ms
Time taken to attain
regulation (from EN=0 to
1) qLR t
ON
2 20 ms
Mode transition
(VREG_SEL = 1 to 0) to
VSEL_STROBE rising edge
teSR_setup
2 us
Mode transition
(VREG_SEL = 0 to 1) to
VSEL_STROBE rising edge
t
SETUP
500
ns
VSEL_STROBE pulse
width t
STRB
1
us
9.2.3 Handling Power Failures
Power failure can occur if main power or battery is removed or brownout occurs.
On-die voltage regulator requires minimum 2.0V at PVDD to ensure 1.8V DVDD for
normal operation.
The SoC does not provide any brownout detection or indicator and relies on external
platform agents to handle brownout and to assert RST_N input pin.
9.3 Reset Behavior
The SoC supports three types of reset:
• Power On Reset
• Cold Reset
• Warm Reset